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About Pocholo Pasicolan
Logic design engineer with over 18 years’ experience specializing in Design-for-test (DFT) design and validation. Possesses technical engineering expertise and ...
Pocholo Pasicolan's Work History
Staff SoC Design Engineer
Intel
Apr 2020 - Present
• DFT integration team within the Xeon server SoC group (XEG)
• Lead embedded memory integration domain
• Responsible for MBIST insertion and integration
• Work on DFT integration for die-to-die interconnect subsystem
Sr. IP Logic Design Engineer
Intel
Sep 2016 - Apr 2020
• DFT integration team within the Xeon server SoC group (XEG)
• Responsible for DFT RTL design and integration for server Cache & Home Agent and Mesh IPs
• Worked with a more diverse set of DFT IPs (i.e. TAP & array BIST controllers, scan and die telemetry elements) and ensured that these functioned in concert to meet HVM testing needs
• Unique design expertise with array test mechanisms for last-level cache and specialized functional modes that improve at-speed coverage
Sr. Graphics Hardware Engineer
Intel
Sep 2008 - Sep 2016
• Graphics hardware design team within the Visual and Parallel Computing Group (VPG)
• Expanded role to include DFT micro-architecture development, RTL design & validation, automation suite construction and post-silicon support
• Responsible for display engine functional HVM testing and compression features (e.g. MISRs & CRCs)
• Co-authored a technical paper that showcased our display engine DFT solution and presented this in an internal company-wide conference (DTTC)
Component Design Engineer
Intel
Jan 2006 - Sep 2008
• Northbridge Chipset Group (CG)
• Started career with DFT RTL design, validation and post-silicon support
• Worked on high-speed serial IO/PHY structural test mode development, die telemetry mechanisms for frequency characterization, and burn-in
Pocholo Pasicolan's Current Work Details
Pocholo Pasicolan's Location
3608 Flora Vista AvenueApartment 329, Santa Clara, United States
Pocholo Pasicolan's Expertise
Logic design engineer with over 18 years’ experience specializing in Design-for-test (DFT) design and validation. Possesses technical engineering expertise and an eye for detail that has proven invaluable during many ASIC development cycles from micro-architecture path-finding to RTL coding & testing and finally to post-silicon debugging. Collaborative leader who has routinely trained and guided colleagues to deliver work that has surpassed project goals and standards.
Staff SoC Design Engineer at Intel Corporation
Pocholo Pasicolan's Current Industry
Intel
Pocholo Pasicolan's Prior Industry
Intel
Pocholo Pasicolan's Education
University of Southern California
University of Southern California Ms , Computer Engineering
Ateneo de Manila University
Ateneo de Manila University Bs , Computer Engineering
Ateneo de Manila University
Ateneo de Manila University Bs , Physics
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