
Pranav Manoor
Build cross geography team for a RISC CPU and drive verification and performance strategy at the top level. Drive... | Santa Clara, California, United States
Pranav Manoor’s Emails pr****@qu****.com
Pranav Manoor’s Phone Numbers No phone number available.
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Pranav Manoor’s Location Santa Clara, California, United States
Pranav Manoor’s Expertise Build cross geography team for a RISC CPU and drive verification and performance strategy at the top level. Drive design/dv activities at block level. Build and lead a world class cross company design verification GPU shader team for AMD’s first mobile initiative. Lead AMD and customer design teams across multiple freeze and successful tape outs. Plan and drive technical roadmaps of small to moderate sized teams in multiple orga of Intel/Qualcomm/SAMSUNG/AMD Wide domain experience - GPU/CPU(x86)/PCIe/DDR/802.11 Front end design verification lead for 10+ years. Currently Driving Power Performance initiatives on graphics shaders. System Verilog, UVM, AVM, C++. Developed Object Oriented verification components like constrained random BFM’s, monitors, checker’s and coverage using UVM constructs from ground up at Intel/Qualcomm. Emulation on Quickturn. Post silicon validation and bringup on several intel chipsets using logic analyzer and oscilloscope. Possess strong leadership/communication/interpersonal/conflict resolution skills.
Pranav Manoor’s Current Industry Amd
Pranav
Manoor’s Prior Industry
Cgi
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Cirrus Logic
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Nimbus Wireless
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Intel
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Qualcomm
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Samsung Austin Semiconductor
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Amd
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Work Experience

Amd
Senior Member Of Technical Staff
Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Samsung Austin Semiconductor
Senior Member Of Technical Staff
Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Senior Member Of Technical Staff
Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Staff Engineer
Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Component Design Engineer
Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Verification Team Lead
Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
System Validation Lead
Mon Mar 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Nimbus Wireless
Design Engineer
Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Dec 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Cirrus Logic
Intern
Tue May 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)
Cgi
Software Engineer
Sun Nov 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)