
Aashish Sharma
Graduate with Honors from University of Southern California with demonstrated history of working in product development professionally at... | San Jose, California, United States
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Aashish Sharma’s Emails aa****@in****.com
Aashish Sharma’s Phone Numbers No phone number available.
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Aashish Sharma’s Location San Jose, California, United States
Aashish Sharma’s Expertise Graduate with Honors from University of Southern California with demonstrated history of working in product development professionally at work and academically at school. Technical Skills: Hardware Descriptive Language: Verilog, VHDL. Programming Language: C, C++,Python scripting, MATLAB scripting, Shell scripting (csh,bash), Tcl Communication paradigm: I2C, UART, AXI, SPI. Simulation Tool : Modelsim, Cadence NCSim. Synopsys VCS Synthesis Tool: Synopsis Design Compiler. Static Timing Analysis: Synopsis Prime Time. Place and Route: Cadence Encounter. Formal Equivalence Check: Cadence Conformal. FPGA Design Suit: Xilinx ISE. Layout : Cadence Virtuoso.
Aashish Sharma’s Current Industry Micron Technology
Aashish
Sharma’s Prior Industry
Iiit Delhi
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Iiit Delhi Stealth Mode Start Up
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University Of Southern California
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Intel
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Micron Technology
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Work Experience

Micron Technology
Senior Design Engineer
Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Senior Product Development Engineer
Wed Apr 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Product Development Engineer
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Fault Isolation Intern
Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
University Of Southern California
Grader for EE457 (Computer System Organisation)
Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Iiit Delhi Stealth Mode Start Up
Research Associate
Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Iiit Delhi
Research Associate
Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Iiit Delhi
Research Intern
Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)