
Abhishek Bit
15+ years of professional experience in the Embedded/VLSI domain. Applications Engineering for GPUs, CPUs and Networking Protocols Pre-silicon and post-silicon... | Mountain View, California, United States
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Abhishek Bit’s Emails ab****@sy****.com
Abhishek Bit’s Phone Numbers No phone number available.
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Abhishek Bit’s Location Mountain View, California, United States
Abhishek Bit’s Expertise 15+ years of professional experience in the Embedded/VLSI domain. Applications Engineering for GPUs, CPUs and Networking Protocols Pre-silicon and post-silicon debug, Firmware development Processor Architectures and Extensions (ARC 600/700/EM/HS/EV), DSP Algorithms, Processor Performance Benchmarking, SoC Integration, IP Validation, FPGA Prototyping Embedded Design Engineering High-speed electronic board design engineering for ARM Cortex M3 / Altera CPLD / FPGA based hardware platforms used to monitor critical sensors and generate / distribute electrical power in UAVs and ground control stations. Specialties: Networking Protocols, PCIe, NV Link, InfiniBand, GPUs Processor architecture, DSP, IP Validation, RTL Design Electronic hardware design (Digital and analog circuits - Altium designer) RTL design and validation (VHDL / Verilog coding for CPLDs / FPGAs using Quartus II / Xilinx ISE) Wireless communication technologies (Ultra Wideband (UWB), Bluetooth) Bluetooth 3.0 and Certified Wireless-USB Terrestrial Digital Video Broadcasting (DVB-T) Video compression algorithms (H.264/AVC, Motion-JPEG2000) In-Circuit Debugging (Trace32)
Abhishek Bit’s Current Industry Nvidia
Abhishek
Bit’s Prior Industry
Freescale Semiconductor
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Institute For Integrated Systems Technical Universiy Of Munich
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Rohde And Schwarz
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Vodafone Group R And D
|
Swiss Uav
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Ambition Infosoft
|
Synopsys
|
Nvidia
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Work Experience

Nvidia
Applications Engineering - Networking Technologies
Mon Jan 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Senior Staff Applications Engineer - Processor and Security IP
Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Staff Applications Engineer - Processor and Security IP
Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Senior II Applications Engineer - Processor IP
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Senior II Applications Engineer - Processor IP
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Senior Applications Engineer - Processor IP
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Corporate Applications Engineer II - Processor IP
Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Ambition Infosoft
Co-owner / Chief Electronics Engineer
Sat Oct 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Swiss Uav
Senior Electrical / Software Design Engineer
Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Swiss Uav
Electrical / Software Design Engineer
Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Vodafone Group R And D
Student Assistant
Sat Nov 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Rohde And Schwarz
Intern
Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Institute For Integrated Systems Technical Universiy Of Munich
Student Assistant
Thu May 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Freescale Semiconductor
Intern
Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)