
Aditya Siripragada
Good in scripting with TCL, PERL, Shell and SKILL. Working experience on Automation for developing layout from CDL Netlist... | Hyderabad, Telangana, India
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Aditya Siripragada’s Emails as****@mi****.com
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Aditya Siripragada’s Location Hyderabad, Telangana, India
Aditya Siripragada’s Expertise Good in scripting with TCL, PERL, Shell and SKILL. Working experience on Automation for developing layout from CDL Netlist without any other Tools support. Good at Physical Verification, and capable of writing custom Calibre SVRF rules. Working experience on Standard Cell QA checks, Generation of LEF abstract views, Validation of Standard Cell Views. Working experience on EM/IR Drop Analysis, Parasitic Extraction and Post Layout Simulations. Capable of implementing automation required for faster library Deliveries in very less time. Sound knowledge on Double, Multi patterning Techniques, issues and resolutions. Work Experience in Standard cell libraries of higher nodes 90nm, 28nm and sub nanometer Technologies 14nm, 7nm, 22FDX. Good Knowledge on FDX and FINFET advanced processes. Worked on different standard cell libraries like BASE,ECO,Low power, High Performance, Level Shifters. Sound knowledge on lower technology concepts and manufacturing issues. Tools Explored: Mentor Calibre Cadence Abstract Cadence Virtuoso Layout Editor Cadence Spectre, Ultrasim, Synopsys HSPICE Synopsys StarRC, Cadence Quantus QRC, Mentor Calibre xACT-3D Bottom Line : Design Automation engineer with standard cell layout development, Quality Analysis Implementation,Post Layout Simulations Experience.
Aditya Siripragada’s Current Industry Micron Technology
Aditya
Siripragada’s Prior Industry
Veda Iit
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Invecas
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Synopsys
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Micron Technology
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Work Experience

Micron Technology
Staff Cad Engineer
Wed Nov 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Micron Technology
Sr. Cad Engineer
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Applications Engineer Ii
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Invecas
Design Automaton Engineer
Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Invecas
Standard Cell Layout Design Engineer
Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Veda Iit
Engineering Trainee
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)