
Alexander Hubris
• Experienced in ASIC design in deep submicron technology starting from specification to layout timing closure: architecture, micro-architecture, RTL... | San Jose, California, United States
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Alexander Hubris’s Emails ah****@mi****.com
Alexander Hubris’s Phone Numbers No phone number available.
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Alexander Hubris’s Location San Jose, California, United States
Alexander Hubris’s Expertise • Experienced in ASIC design in deep submicron technology starting from specification to layout timing closure: architecture, micro-architecture, RTL coding with clock gating, synthesis, floorplanning, DFT, BIST, place and route, STA, and LEC • Experienced in Hardware Modeling on various technologies and platform with strong emphasis on Cadence Palladium emulation • Experienced in developing system verification methodology for testing SOC in emulation • Experienced on development and documentation of design flows and methodology • Experienced in ASIC bring up, tester program debug, test board development and design for volume production and prototyping of ASIC related products • 7M+ chips shipped for SCDMA chip, 2M+ for DOCSIS modulator w/ 500K+ shipping/ Quarter • 30M+ chips shipped for SSD controller chip w/ over 2M+ shipping/Quarter • Experienced on various hardware lab instruments: Cadence Palladium Emulator, Spectrum Analyzers, Function Generators, Digital Multimeters, Signal Generators, Oscilloscopes, Logic Analyzers, and other test equipment Specialties: LDPC Encoder/Decoder, Emulation Hardware Modeling and SOC System Verification, ASIC Design and Test including Production Testing, SSD ■ Hold 7+ patents or patent pending technologies in error correction and compression for Flash and video processor field
Alexander Hubris’s Current Industry Micron Technology
Alexander
Hubris’s Prior Industry
Lsi Logic
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Terayon
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Ati
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Ati Research
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Novafora
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Sandforce
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Micron Technology
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Work Experience

Micron Technology
Principal ASIC Design Engineer
Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Sandforce
Principal Engineer
Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Novafora
Sr. Member of Technical Staff & Emulation Manager
Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Ati
Member of Technical Staff
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Ati Research
Member of Technical Staff
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Terayon
Member of Technical Staff
Sun Jan 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi Logic
Sr Cad Engineer
Fri Jan 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time)