
Alexey Lopich
- Results-driven technical lead and eng. manager, system engineer and ASIC/FPGA Design expert - Extensive experience in defining, developing... | Manchester, England, United Kingdom
*50 free lookup(s) per month.
No credit card required.
Alexey Lopich’s Emails al****@ap****.co
Alexey Lopich’s Phone Numbers 44179340****
Social Media
Alexey Lopich’s Location Manchester, England, United Kingdom
Alexey Lopich’s Expertise - Results-driven technical lead and eng. manager, system engineer and ASIC/FPGA Design expert - Extensive experience in defining, developing and delivering complex and innovative semiconductor projects, from concept to the field - Proven track record of managing multi-site, multi-discipline engineering teams. Delivery of high-quality product - Over 20 years of hands-on experience leading research, architecture development , partitioning, design (full-custom ASIC development, FPGA and system integration), functional verification, synthesis, P&R and validation. Strong knowledge of embedded system design (SW/FW development). Over 8 years of managing teams,. - Team player with good communication skills. Self-starter, highly motivated and hardworking
Alexey Lopich’s Current Industry Intel
Alexey
Lopich’s Prior Industry
Ntlab
|
University Of Manchester
|
Apical
|
Arm
|
Intel
Not the Alexey Lopich you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Intel
Director of Engineering
Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Engineering Manager
Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Arm
Team Manager and Technical Lead, Vision Prototyping
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Apical
Technical and Product Lead
Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Apical
Senior Design Engineer/Architect
Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
University Of Manchester
Research Associate
Fri Sep 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Ntlab
Digital Design Engineer
Thu May 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)