Allen Tseng
Skills and Knowledge 1. IC Design : Verilog, Synthesis, DFT tools and flow, BIST circuit, formality, ATPG Diagnosis assist design 2.... | Hsinchu City, Hsinchu City, Taiwan
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Allen Tseng’s Emails nh****@ts****.com
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Allen Tseng’s Location Hsinchu City, Hsinchu City, Taiwan
Allen Tseng’s Expertise Skills and Knowledge 1. IC Design : Verilog, Synthesis, DFT tools and flow, BIST circuit, formality, ATPG Diagnosis assist design 2. IC Testing : ATPG ( Tmax, FastScan, EncounterTest ) : coverage enhancement, stuck-at fault, transition fault, bridge fault, Small Delay Detection ( SDD ) 3. Design for testability : DFT Scan insertion, scan compression , logic BIST, Failure Diagnosis, Design for Process Variation monitor, MBIST/MBISR 4. ATE : HP93000/HP83000 test program development 5. Assembly : Allegro SPB, Package level IR analysis (Apache/Optimal), stack IC package/SiP knowledge, 6. 3DIC : 3DIC testing, design flow, structure, DFT 7. Integration of Design, testing & assembly : Many testing experience and quite familiar to the completed IC design flow from design, assembly to testing. Base on the angle of design to improve testing procedure and reduce testing cost. Using testing experience enhance design testability and DFT capacity. For advance process ( 40nm/ 28nm/20nm ), chip testability and DFT is more and more important than before. It’s my advantage to shorten the time from design site to mass production based on previous experience. Personality : Omni-bearing and Versatile / Innovative / High absorbency
Allen Tseng’s Current Industry 台灣積體電路製造股份有限公司
Allen
Tseng’s Prior Industry
Mosel Vitelic
|
Chipmos Tech
|
Avid
|
Smediatech
|
Tsmc
|
台灣積體電路製造股份有限公司
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Work Experience
台灣積體電路製造股份有限公司
Senior Manager
Thu Jun 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Tsmc
Manager
Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Smediatech
Assistant Manager
Fri Oct 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Avid
Senior Digital Ic Design Engineer
Mon Jul 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Chipmos Tech
Project Management Engineer
Tue Jul 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Mosel Vitelic
Senior Testing Engineer
Tue Aug 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Allen Tseng Email Addresses
FAQ About Allen Tseng
-
Allen Tseng is located at
Hsinchu City, Hsinchu City, Taiwan -
Allen Tseng is a
Skills and Knowledge 1. IC Design : Verilog, Synthesis, DFT tools and flow, BIST circuit, formality, ATPG Diagnosis assist design 2. IC Testing : ATPG ( Tmax, FastScan, EncounterTest ) : coverage enhancement, stuck-at fault, transition fault, bridge fault, Small Delay Detection ( SDD ) 3. Design for testability : DFT Scan insertion, scan compression , logic BIST, Failure Diagnosis, Design for Process Variation monitor, MBIST/MBISR 4. ATE : HP93000/HP83000 test program development 5. Assembly : Allegro SPB, Package level IR analysis (Apache/Optimal), stack IC package/SiP knowledge, 6. 3DIC : 3DIC testing, design flow, structure, DFT 7. Integration of Design, testing & assembly : Many testing experience and quite familiar to the completed IC design flow from design, assembly to testing. Base on the angle of design to improve testing procedure and reduce testing cost. Using testing experience enhance design testability and DFT capacity. For advance process ( 40nm/ 28nm/20nm ), chip testability and DFT is more and more important than before. It’s my advantage to shorten the time from design site to mass production based on previous experience. Personality : Omni-bearing and Versatile / Innovative / High absorbency 台灣積體電路製造股份有限公司 -
Allen Tseng currently works in the
台灣積體電路製造股份有限公司 -
Allen Tseng specializes in
Skills and Knowledge 1. IC Design : Verilog, Synthesis, DFT tools and flow, BIST circuit, formality, ATPG Diagnosis assist design 2. IC Testing : ATPG ( Tmax, FastScan, EncounterTest ) : coverage enhancement, stuck-at fault, transition fault, bridge fault, Small Delay Detection ( SDD ) 3. Design for testability : DFT Scan insertion, scan compression , logic BIST, Failure Diagnosis, Design for Process Variation monitor, MBIST/MBISR 4. ATE : HP93000/HP83000 test program development 5. Assembly : Allegro SPB, Package level IR analysis (Apache/Optimal), stack IC package/SiP knowledge, 6. 3DIC : 3DIC testing, design flow, structure, DFT 7. Integration of Design, testing & assembly : Many testing experience and quite familiar to the completed IC design flow from design, assembly to testing. Base on the angle of design to improve testing procedure and reduce testing cost. Using testing experience enhance design testability and DFT capacity. For advance process ( 40nm/ 28nm/20nm ), chip testability and DFT is more and more important than before. It’s my advantage to shorten the time from design site to mass production based on previous experience. Personality : Omni-bearing and Versatile / Innovative / High absorbency -
Allen Tseng speaks the following languages:
No languages available. -
Allen Tseng has prior experience in the following industries:
Tsmc , Smediatech , Avid , Chipmos Tech , Mosel Vitelic -
Allen Tseng has the following professional experience:
台灣積體電路製造股份有限公司 , Tsmc , Smediatech , Avid , Chipmos Tech , Mosel Vitelic . -
You can view Allen Tseng’s
LinkedIn profile at LinkedIn URL. -
Allen Tseng’s work email addresses are
[email protected] . -
Allen Tseng works at
台灣積體電路製造股份有限公司
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