
Arindrajit Ghosh
Overall 21.5 years of experience. As a Circuit Design Engineer with 18+ years of relevant industry experience in... | Austin, Texas, United States
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Arindrajit Ghosh’s Location Austin, Texas, United States
Arindrajit Ghosh’s Expertise Overall 21.5 years of experience. As a Circuit Design Engineer with 18+ years of relevant industry experience in memory design. Junior Research Fellow with nearly 3.5 years of research experience in ADC/DAC. Seeking a challenging professional growth oriented position, investing time and energy in team spirit, to meet the challenges and rise with and for the organization in the field of chip design. Design Experiences: • Circuit Design & Architecture Read only Memory, Two-Port-Register-File, Multi-Port Register-File. • Memory Design, Characterization and Verification flow. • Critical Path Design, Marginality Analysis, Mismatch & Statistically Analysis. • Parasitic Extraction of Full Memory / Memory Leaf Cell (RC / C). • Memory Characterization flows for timing, power,Leakage,Capacitance. • Familiarity with full flow/Methodology for compiler design. • Design & Analysis of various Memory compiler like high-density (HD), ultra high density (UHD), low Vmin (LV), low leakage (LL) Register Files.
Arindrajit Ghosh’s Current Industry Intel
Arindrajit
Ghosh’s Prior Industry
Cad Lab
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Intel
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Work Experience

Intel
IP Lead
Thu Mar 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Sr. Design Engineer
Sun Mar 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Design Engineer
Sat Jul 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Cad Lab
Junior Research Fellow
Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)