Arun Balachandar

Arun Balachandar

19+ years of Proven Technical Expertise on End2End Pre/Post Silicon verification and System validation. Presently working at Intel.... | Bengaluru, Karnataka, India

*50 free lookup(s) per month.

No credit card required.

Arun Balachandar’s Emails

Arun Balachandar’s Phone Numbers

Social Media

Arun Balachandar’s Location

Arun Balachandar’s Expertise

Arun Balachandar’s Current Industry

Arun Balachandar’s Prior Industry

Not the Arun Balachandar you were looking for?

Find accurate emails & phone numbers for over 700M professionals.

Work Experience

Intel

Director Of Engineering

Sun Oct 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Engineering Manager

Fri Mar 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Qualcomm

Senior Staff Manager/Engineer

Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Qualcomm

Tech Lead : Product & Test Engineering / Sim Team - Karmic

Thu Mar 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Texas Instruments

Domain Manager : Silicon Test Development - Karmic

Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Karmic Design Centre

Researcher ( Productization )

Mon Dec 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)

Texas Instruments

Tech Lead : Silicon Validation And Verification - Karmic

Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Nov 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Texas Instruments

Tech Lead : Ip Design, Integration, Pm - Karmic

Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Texas Instruments

Tech Lead Sram : Front End Modeling (Dft,Verilog) - Karmic

Tue Mar 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)

Texas Instruments

Layout Engineer : Member Of Asic Library Development - Karmic

Wed Sep 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)

Bharat Electronics

Internship Trainee

Fri Dec 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)

Bharat Electronics

Internship Trainee

Thu Jul 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Director of Engineering

— Present

Skills

Languages

No languages available.