Bhavit Kaushik

Bhavit Kaushik

Passinate Timing Signoff Engineer with a decade experience in subsystem and partition timing closure & methodology, timing signoff... | Bengaluru, Karnataka, India

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Work Experience

Intel

Senior Soc Design engineer

Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Qualcomm

Senior Engineer

Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Tata Elxsi

Physical Design Engineer

Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Rv Vlsi Design Center

Physical Design Engineer Trainee

Sat Nov 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Csir Ceeri

Trainee Scientist

Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Tata Consultancy Services

Assistant System Engineer

Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

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