Chaitanya Anandkar
-Worked on Latest Technology nodes like 14nm, 10nm and 7nm. -Well versed with Placement and Routing at Full chip... | Intel, NO 17, India
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Chaitanya Anandkar’s Emails ch****@in****.com
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Chaitanya Anandkar’s Location Intel, NO 17, India
Chaitanya Anandkar’s Expertise -Worked on Latest Technology nodes like 14nm, 10nm and 7nm. -Well versed with Placement and Routing at Full chip Level. -Good Knowledge on Floor planning, Timing Analysis, CTS. -Hands-on experience of Physical Verification, Reliability Verification and Performance Verification fixes in Layout. -Good Knowledge about Timing Fixes in Layout. -Basic Knowledge on using Cadence Virtuoso Tool. -Have Basic Knowledge of VHDL and Verilog. -Have Basic TCL Scripting skills for Automation. -Ready to learn and adapt in different domains.
Chaitanya Anandkar’s Current Industry Intel
Chaitanya
Anandkar’s Prior Industry
Intel
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Work Experience
Intel
Digital Design Engineer
Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Physical Design Intern
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Physical Design Engineer
— PresentSkills
Languages
Chaitanya Anandkar Email Addresses
FAQ About Chaitanya Anandkar
-
Chaitanya Anandkar is located at
Intel, NO 17, India -
Chaitanya Anandkar is a
-Worked on Latest Technology nodes like 14nm, 10nm and 7nm. -Well versed with Placement and Routing at Full chip Level. -Good Knowledge on Floor planning, Timing Analysis, CTS. -Hands-on experience of Physical Verification, Reliability Verification and Performance Verification fixes in Layout. -Good Knowledge about Timing Fixes in Layout. -Basic Knowledge on using Cadence Virtuoso Tool. -Have Basic Knowledge of VHDL and Verilog. -Have Basic TCL Scripting skills for Automation. -Ready to learn and adapt in different domains. Intel -
Chaitanya Anandkar currently works in the
Intel -
Chaitanya Anandkar specializes in
-Worked on Latest Technology nodes like 14nm, 10nm and 7nm. -Well versed with Placement and Routing at Full chip Level. -Good Knowledge on Floor planning, Timing Analysis, CTS. -Hands-on experience of Physical Verification, Reliability Verification and Performance Verification fixes in Layout. -Good Knowledge about Timing Fixes in Layout. -Basic Knowledge on using Cadence Virtuoso Tool. -Have Basic Knowledge of VHDL and Verilog. -Have Basic TCL Scripting skills for Automation. -Ready to learn and adapt in different domains. -
Chaitanya Anandkar speaks the following languages:
No languages available. -
Chaitanya Anandkar has prior experience in the following industries:
Intel -
Chaitanya Anandkar has the following professional experience:
Intel , Intel , Intel . -
You can view Chaitanya Anandkar’s
LinkedIn profile at LinkedIn URL. -
Chaitanya Anandkar’s work email addresses are
[email protected] . -
Chaitanya Anandkar works at
Intel
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