Chris Papalias

Chris Papalias

No headline available | South San Francisco, California, United States

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Work Experience

Intel

ESD Engineer

Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Thermo Fisher Scientific

Sr. Staff Engineer

Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Life Technologies

Sr. Staff Engineer

Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Analog Rails

Analog Design Engineer

Fri Jan 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Eastman Kodak

Analog Design Engineer

Wed Sep 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)

Tec

Design Engineer

Tue Jan 01 1991 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time)

National Semiconductor

Staff Design Engineer

Tue Sep 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

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