Collin Yu
In charge of block level physical design through entire ASIC flow from RTL to GDS2. Includes synthesis, PNR,... | San Francisco, San Francisco, United States
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Collin Yu’s Location San Francisco, San Francisco, United States
Collin Yu’s Expertise In charge of block level physical design through entire ASIC flow from RTL to GDS2. Includes synthesis, PNR, timing closure, power closure and physical verification Experience in: ◦ Low power and power gated design ◦ High speed DDR PHY IP implementation ◦ Manual bus routing and length based buffering ◦ Library management and PNR flow management ◦ Top level, block level and IO timing closure ◦ Global Foundries 28nm and Samsung 28nm technologies ◦ PERL and TCL scripting for compiling and analyzing data. Developed a “Triggered Read” system for the readout of electron tracks on CCD sensors using hardware such as ASICs and a Xilinx FPGA board and software tools such as QT creator, Xilinx ISE and EDK Design Suite.
Collin Yu’s Current Industry Uniquify Inc
Collin
Yu’s Prior Industry
U.C. Berkeley
|
Uniquify Inc
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Work Experience
Uniquify Inc
ASIC Design Engineer
Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
U.C. Berkeley
Hardware Interface Engineer
Sun Aug 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Collin Yu Email Addresses
FAQ About Collin Yu
-
Collin Yu is located at
San Francisco, San Francisco, United States -
Collin Yu is a
In charge of block level physical design through entire ASIC flow from RTL to GDS2. Includes synthesis, PNR, timing closure, power closure and physical verification Experience in: ◦ Low power and power gated design ◦ High speed DDR PHY IP implementation ◦ Manual bus routing and length based buffering ◦ Library management and PNR flow management ◦ Top level, block level and IO timing closure ◦ Global Foundries 28nm and Samsung 28nm technologies ◦ PERL and TCL scripting for compiling and analyzing data. Developed a “Triggered Read” system for the readout of electron tracks on CCD sensors using hardware such as ASICs and a Xilinx FPGA board and software tools such as QT creator, Xilinx ISE and EDK Design Suite. Uniquify Inc -
Collin Yu currently works in the
Uniquify Inc -
Collin Yu specializes in
In charge of block level physical design through entire ASIC flow from RTL to GDS2. Includes synthesis, PNR, timing closure, power closure and physical verification Experience in: ◦ Low power and power gated design ◦ High speed DDR PHY IP implementation ◦ Manual bus routing and length based buffering ◦ Library management and PNR flow management ◦ Top level, block level and IO timing closure ◦ Global Foundries 28nm and Samsung 28nm technologies ◦ PERL and TCL scripting for compiling and analyzing data. Developed a “Triggered Read” system for the readout of electron tracks on CCD sensors using hardware such as ASICs and a Xilinx FPGA board and software tools such as QT creator, Xilinx ISE and EDK Design Suite. -
Collin Yu speaks the following languages:
No languages available. -
Collin Yu has prior experience in the following industries:
Uniquify Inc , U.C. Berkeley -
Collin Yu has the following professional experience:
Uniquify Inc , U.C. Berkeley . -
You can view Collin Yu’s
LinkedIn profile at LinkedIn URL. -
Collin Yu’s work email addresses are
[email protected] . -
Collin Yu works at
Uniquify Inc
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