
Darren Lasko
Exceptional computer engineer and security architect specializing digital ASIC, system-on-a-chip (SoC), and CPU architecture/design with a strong background... | Raleigh, North Carolina, United States
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Darren Lasko’s Emails da****@mi****.com
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Darren Lasko’s Location Raleigh, North Carolina, United States
Darren Lasko’s Expertise Exceptional computer engineer and security architect specializing digital ASIC, system-on-a-chip (SoC), and CPU architecture/design with a strong background in security/cryptography, server-class SoC architecture, data storage devices (SSD/HDD), and networking. Summary of qualifications: - Skilled security architect with a proven history of architecting solutions to address specific threats; experience in both hardware and firmware security (JTAG port access control, “secure boot” via cryptographic verification of firmware, security development lifecycle, etc.) - Seasoned ASIC/SoC/FPGA designer with a history of high quality designs - Experience in networking products and microprocessor-based hardware design - Significant contributor to the various phases of product development: product definition/requirements, general architecture definition, hardware/firmware partitioning and interface definition, detailed engineering specification, design and implementation of hardware (and some firmware), design verification, RTL synthesis, static timing analysis - Proficient in the Verilog hardware description language and various EDA tools - Strong knowledge of a wide variety of cryptographic algorithms/protocols and their application, including US Government-approved security specifications such as the Federal Information Processing Standards (FIPS) and NIST 800 series of Special Publications (SPs) - Key contributor to the Trusted Computing Group (TCG) Storage specifications for self-encrypting drive technology - Self-motivated to produce excellent results with minimal supervision
Darren Lasko’s Current Industry Nvidia
Darren
Lasko’s Prior Industry
Idealogy
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Cadence Design Systems
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Vitesse Semiconductor
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Fujitsu
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Toshiba
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Intel
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Qualcomm
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Nvidia
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Microsoft
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Work Experience

Nvidia
Principal Engineer, Hardware Security
Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Microsoft
Principal Hardware Security Architect
Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Nvidia
Principal Security Engineer
Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Principal Engineer
Fri Nov 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Principal Storage Security Architect
Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Nov 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Toshiba
Principal Engineer, SoC Development
Thu Oct 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Fujitsu
Principal Engineer, VLSI Design
Sun Dec 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Vitesse Semiconductor
Senior Member of Technical Staff
Tue Jul 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Senior Consulting Engineer
Mon Jul 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)
Idealogy
Staff Engineer II
Sun Jan 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time)