
Deepak Kawathale
● Hands-on experience in FPGA Design using Xilinx Vivado 2019.1,ISE 14.7 & Microsemi's Libero and Modelsim for simulation,... | Hyderabad, Hyderabad, India
*50 free lookup(s) per month.
No credit card required.
Deepak Kawathale’s Emails de****@mi****.com
Deepak Kawathale’s Phone Numbers No phone number available.
Social Media
Deepak Kawathale’s Location Hyderabad, Hyderabad, India
Deepak Kawathale’s Expertise ● Hands-on experience in FPGA Design using Xilinx Vivado 2019.1,ISE 14.7 & Microsemi's Libero and Modelsim for simulation, Identify for debugging ● Hands-on experience in FPGA based RTL Implementation using VHDL/Verilog and TCL scripting ● Worked on ZYNQ (ZC7020) SOC, KINTEX-7 and KINTEX UltraScale Xilinx FPGA’s and CPLD (XC9536XL), Microsemi's RTG4,SmartFusion,IGLOO2 and Polarfire FPGA's ● Hands on experience on CDC and Linting, timing verification ● Scripting using TCL and perl ● Good understanding of JESD204B, DDR and PCIe ● Hands on experience of JESD204B Interopbility tests with TI and Analog ADCs ● Experience in digital front end design and interfacing with various digital modules ● Experience in Design and development of high speed systems on FPGA ● Micro architecture designing and timing analysis ● Compilation (Synthesis, UCF creation, timing closure, Place and route) ● Sound Knowledge on high speed interfaces such as AMBA-AXI interface ● Implemented various DSP algorithms using VHDL/Verilog ● Used DSP block set such as DDS, FFT, FIR, and CIC of Xilinx IDE ● Hands-on experience in system level integration, testing and debugging ● Board bring-up and Hardware debugging ● Experience in interfacing industry standard high speed ADC, Clock synthesizer and DAC with FPGA ● Implementation of designs with multiple clock domains ● Familiarity with lab test equipments such as logic analyzer, Oscilloscope, function generators and pattern generator
Deepak Kawathale’s Current Industry Microchip Technology
Deepak
Kawathale’s Prior Industry
Microchip Technology
|
Maven Silicon
|
Qualitat Systems
|
Core Scientific System
|
Microsemi
Not the Deepak Kawathale you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Microchip Technology
Senior Engineer I - Design
Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Microchip Technology
Design Engineer - Ii (Fpga)
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Microsemi
Fpga Consultant
Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Core Scientific System
Fpga Design Engineer
Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualitat Systems
Trainee Vlsi Design Engineer
Tue Oct 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Maven Silicon
Vlsi (Asic) Verification And Design Trainee
Sat Sep 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Microchip Technology
Senior Engineer I - Design
— Present