
Digesh Patel
• Hands on experience in Function Verification using Systemverilog and advance verification methodology OVM, UVM. • Hands on experience in using... | Bengaluru, Karnataka, India
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Digesh Patel’s Emails di****@ta****.co
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Digesh Patel’s Location Bengaluru, Karnataka, India
Digesh Patel’s Expertise • Hands on experience in Function Verification using Systemverilog and advance verification methodology OVM, UVM. • Hands on experience in using EDA tools and debugging. • Worked on various verification projects having complexity ranging from IP level to system level. • Experience in migrating verification database for various EDA vendors. • Experience in migrating OVM to UVM. • Hands on experience in Coverage, SVA, Feature extraction and Testplan development. • Experience in setting up and debugging Gate level simulations. Technical Skills: Programming Language: System Verilog, Verilog, VHDL, C , C++ Verification Methodologies: OVM, UVM EDA Tools: Ncsim, Questa Sim, Verdi, Questasim Familiar Protocols: PCIe, AXI4, USB2.0, H.264, SD4, LPDDR3, DFI, OTP Scripting : Perl, Makefile Revision Management: SVN, Perforce, CVS
Digesh Patel’s Current Industry Broadcom
Digesh
Patel’s Prior Industry
Merchant Engineering College
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Tikona Digital Networks
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Tata Elxsi
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Rambus
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Lsi An Avago Technologies
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Broadcom
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Work Experience

Broadcom
R&D Enginner Ic Verification 5
Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Broadcom
R&D Engineer Ic Verification-4
Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
R&D Engineer Ic Verification-3
Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi An Avago Technologies
R&D Engineer Ic Verification-3
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Rambus
Member Of Technical Staff - Logic Verification
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Tata Elxsi
Senior Verification Engineer
Thu Nov 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Tata Elxsi
Verification Engineer
Mon Nov 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Tikona Digital Networks
Operations Engineer
Thu Oct 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Merchant Engineering College
Lecturer
Wed Jul 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)