
Dineshkumar Mylsamy
Electrical Engineering Graduate specialized in Digital VLSI Design at Arizona State University, actively seeking full-time opportunities in Hardware... | Austin, Texas, United States
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Dineshkumar Mylsamy’s Emails dm****@ca****.com
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Dineshkumar Mylsamy’s Location Austin, Texas, United States
Dineshkumar Mylsamy’s Expertise Electrical Engineering Graduate specialized in Digital VLSI Design at Arizona State University, actively seeking full-time opportunities in Hardware design. Have a good knowledge of Digital Design concepts, Verilog, Physical Design flow and working knowledge of EDA tools like Synopsis Design Compiler, Primetime, Cadence Virtuoso, Cadence Encounter & Innovus. I have a good knowledge of memory design like DRAM, SRAM and Register File Design. I have 2 year and 5 months of work experience at Ford Motor Company as a Test Analyst which helped me to hone my analytical and problem-solving skills. > Domains of expertise: Digital Systems and Circuit Design, Analog Integrated Circuits > EDA Tools (Backend): Cadence Virtuoso, StarRC, RTL Compiler For Synthesis, Encounter > HDL Languages: Verilog, SystemVerilog > Programming: Matlab, C/C++ > Scripting Languages: TCL, PERL > Operating Systems of familiarity: Windows, Linux, Android > Related Coursework: Spring 2017: Digital Systems and Circuit Design, Analog Integrated Circuits, Low Power Bio-Electronics Fall 2017: VLSI Design, Hardware Acceleration and FPGA, Constructionist Approach to Microprocessor Design Spring 2018: Computer Architecture, Advanced Analog Integrated Circuits, Neuromorphic Computing Hardware Design
Dineshkumar Mylsamy’s Current Industry Cadence Design Systems
Dineshkumar
Mylsamy’s Prior Industry
Ford Motor
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Arizona State University
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Cadence Design Systems
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Work Experience

Cadence Design Systems
Lead Product Engineer
Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Cadence Design Systems
Lead Product Engineering
Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Product Engineer II
Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Arizona State University
Graduate Summer Assistant
Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Arizona State University
Graduate Teaching Assistant
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Arizona State University
Graduate Service Assistant - Grader
Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Arizona State University
SDFC Membership Services Supervisor
Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Ford Motor
Automation Test Analyst
Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)