
Divya Kustagi
6+ years of rich experience in Custom IC Design, particularly Interface Circuit Design, with focus on: • IO library... | Seattle, Washington, United States
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Divya Kustagi’s Location Seattle, Washington, United States
Divya Kustagi’s Expertise 6+ years of rich experience in Custom IC Design, particularly Interface Circuit Design, with focus on: • IO library designs and verification (LVCMOS, I2C, Over-voltage IOs, LVDS, DDRs and MPHY Protocols) with Aging, Reliability & Signal Integrity related exposure. • Generation and Validation of Timing models (Single ended / Differential), IBIS and Functional models. • ESD Custom design / Overall Strategy for various IO types • Completed the following Graduate level courses at the University of Washington : Complex Digital VLSI System Design (EE525 : VLSI II); Linear Integrated Circuits Design (EE538) for Winter Quarter 2020. Exposure to Process Nodes : From 130nm down to 4nm finfet in various foundries Tools Proficiency: • Cadence IC Design/Virtuoso Suite, Solido Suite, Liberate, T2B, iVerilog • Exposure to: Synopsys VCS, Design Compiler, IC Compiler, Primetime STA/SI, Formality, Calibre DRC/LVS/xRC • Customer specific tools/flows for Timing, Reliability Verification, Gradual Aging and Statistical Analysis Programming: • Python, Skill, Perl and Tcl scripting; Shell / Ocean scripting • SystemVerilog, VerilogA modelling; C programming Technical Knowledge / Expertise : • DDRs (DDR2/3/4, LPDDR3/4), SSTL-HSTL, MPHY Protocols and design care-abouts, LVDS Tx-Rx Design aspects, Calibration • ESD, Power Bus design for various IO types • Control Systems, Signal/Power Integrity, Jitter (RJ, Phase Noise, etc) • FinFet Design & key Care-abouts, Aging Effects (HCI, BTI, Self-heating)
Divya Kustagi’s Current Industry Intel
Divya
Kustagi’s Prior Industry
Sankalp Semiconductor
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Qualcomm
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Intel
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Work Experience

Intel
SoC Analog Design Engineer
Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Senior Engineer
Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Sankalp Semiconductor
Senior Design Engineer
Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Sankalp Semiconductor
Design Engineer
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)