
Don Ticarich
I have focused on researching and implementing verification methodologies for ASICs and SoCs. I have held roles in... | 13876 Packard Terrace, Delray Beach, United States
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Don Ticarich’s Location 13876 Packard Terrace, Delray Beach, United States
Don Ticarich’s Expertise I have focused on researching and implementing verification methodologies for ASICs and SoCs. I have held roles in the semiconductor, EDA and consulting industry. Specialties: Design & Verification Tools: Cadence: NCSim, Synopsys: VCS, Mentor: QuestaSim, Interconnect Work Bench, AMBA VIP Design & Verification Languages: SystemVerilog, Vera, Verilog, SystemC, C/C++, PSL, SVA, PLI Verification Methodologies & Methodology Libraries: Constrained Random Verification (CRV), Coverage Driven Verification (CDV), Assertion Based Verification (ABV), VMM, RVM, OVM, UVM
Don Ticarich’s Current Industry Siemens Eda
Don
Ticarich’s Prior Industry
Motorola
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Florida Atlantic University
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Harris Semiconductor
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Cadence Design Systems
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Independent Consulting
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Sonics
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Qthink Ic Design
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Juniper Networks
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Rockwell Collins
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Intel
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Mentor Graphics
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Siemens Digital Industries Software
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Siemens Eda
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Work Experience

Siemens Eda
Verification Application Engineer - Emulation
Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Siemens Digital Industries Software
Verification Consultant at Siemens EDA
Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mentor Graphics
Verification Consultant
Wed Mar 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Cadence Design Systems
Verification Application Engineer - Verification Consultant
Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
SoC Verification Engineer
Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Rockwell Collins
Verification Engineer
Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Juniper Networks
Verification Engineer
Sun Mar 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Qthink Ic Design
Design & Verification Group Manager & Consultant
Sun Apr 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Nov 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Sonics
Verification Engineer
Wed Nov 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Independent Consulting
Consultant
Mon Mar 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Verification Application Engineer
Wed Jul 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Harris Semiconductor
CAD / CAE Engineer
Tue Apr 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)
Florida Atlantic University
Research Project Consultant
Mon Jan 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)
Motorola
CAD / CAE Engineer
Thu Sep 01 1983 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time)