Durgesh Srivastava

Durgesh Srivastava

Technical * Data Center Infrastructure, Disaggregated architecture, Memory Pooling, Accelerator as a Peer, Fabric Management * Linux kernel module for... | 10379 Krista Court, Cupertino, United States

*50 free lookup(s) per month.

No credit card required.

Durgesh Srivastava’s Emails

Durgesh Srivastava’s Phone Numbers

Social Media

Durgesh Srivastava’s Location

Durgesh Srivastava’s Expertise

Durgesh Srivastava’s Current Industry

Durgesh Srivastava’s Prior Industry

Not the Durgesh Srivastava you were looking for?

Find accurate emails & phone numbers for over 700M professionals.

Work Experience

Mips

Chief Technology Officer

Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Universal Chiplet Interconnect Express

Board Member representing NVIDIA

Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)

Nvidia

Data Center Product Architect and Senior Director

Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)

Cloud And Automotive Infrastructure Team Intel

Data Center Infrastructure Systems Architect and Senior Principal Engineer

Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Automotive Solutions Division Intel

Cloud Infrastructure Architect for Autonomous Driving and Senior Principal Engineer

Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Embedded And Iot Division Intel

Platform and Software Lead Architect - Intel In-Vehicle Infotainment solution

Mon Nov 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Cpu Soc And Chipset Intel

CHIEF ARCHITECT and PRODUCT ENGINEER

Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)

Xeon And Itanium Architecture Intel

Systems and Silicon Architect

Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

No languages available.