
Durgesh Srivastava
Technical * Data Center Infrastructure, Disaggregated architecture, Memory Pooling, Accelerator as a Peer, Fabric Management * Linux kernel module for... | 10379 Krista Court, Cupertino, United States
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Durgesh Srivastava’s Emails du****@nv****.com
Durgesh Srivastava’s Phone Numbers No phone number available.
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Durgesh Srivastava’s Location 10379 Krista Court, Cupertino, United States
Durgesh Srivastava’s Expertise Technical * Data Center Infrastructure, Disaggregated architecture, Memory Pooling, Accelerator as a Peer, Fabric Management * Linux kernel module for hot-cold pages, Memory Management, Performance profiling, HW-SW co-enabling, Autonomous Driving Data Center * Server SoC architecture, Xeon/Atom SoC architecture, Cache and memory coherency silicon Debug, FPGA prototyping Leadership * Product Requirements, Definition and Execution, Roadmap definition, Bringing order out of chaos, and Coach, and Mentor
Durgesh Srivastava’s Current Industry Mips
Durgesh
Srivastava’s Prior Industry
Xeon And Itanium Architecture Intel
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Cpu Soc And Chipset Intel
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Embedded And Iot Division Intel
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Automotive Solutions Division Intel
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Cloud And Automotive Infrastructure Team Intel
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Nvidia
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Universal Chiplet Interconnect Express
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Mips
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Work Experience

Mips
Chief Technology Officer
Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Universal Chiplet Interconnect Express
Board Member representing NVIDIA
Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Nvidia
Data Center Product Architect and Senior Director
Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Cloud And Automotive Infrastructure Team Intel
Data Center Infrastructure Systems Architect and Senior Principal Engineer
Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Automotive Solutions Division Intel
Cloud Infrastructure Architect for Autonomous Driving and Senior Principal Engineer
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Embedded And Iot Division Intel
Platform and Software Lead Architect - Intel In-Vehicle Infotainment solution
Mon Nov 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Cpu Soc And Chipset Intel
CHIEF ARCHITECT and PRODUCT ENGINEER
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Xeon And Itanium Architecture Intel
Systems and Silicon Architect
Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)