
Eoin Carroll
Twitter @w3knight Very passionate about innovating defense strategies and security models to combat credible threats/attack classes. Experienced across the... | Ireland
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Eoin Carroll’s Emails eo****@te****.toyota
Eoin Carroll’s Phone Numbers No phone number available.
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Eoin Carroll’s Location Ireland
Eoin Carroll’s Expertise Twitter @w3knight Very passionate about innovating defense strategies and security models to combat credible threats/attack classes. Experienced across the platform stack from silicon to web. Core Technical Skills: Threat modeling, secure platform design, memory forensics, vulnerability and exploit analysis, reverse engineering, product engineering, OS internals and incident response. About me: The constant challenge of adapting to new threats and learning new technologies is what attracted me to cyber security. Creating a more trustworthy digital ecosystem for today and tomorrow is what drives me. Committed to building a pipeline of world class security talent in Ireland through partnering with Cork Institute of Technology and Cyber Ireland. The value I bring is the rare and creative hybrid skillset of Architect/Engineer/Researcher to build defensive strategies from offensive research by breaking down the mechanics of complex platform security models, vulnerabilities and threats to their primitives to engineer trustworthy, resilient, dependable systems. 20 years of diverse experience, from electronic engineering to a variety of offensive and defensive security roles. For the first decade of my career I worked as an electronic engineer in both the semiconductor and medical device industries, gaining a wealth of engineering and risk experience. During the second decade I've been building my career in platform security through Endpoint product security, reverse engineering critical industry vulnerabilities and designing exploit protections as a Principal Engineer @office of CTO for McAfee. My domain expertise is Endpoint and Network protocols where I analyze the Threatscape from a vulnerability, exploit and malware TTP perspective to engineer defense solutions. In addition, I've lead Product Security teams, mentored many Product Security Engineers/Architects and supported local universities to keep their security curriculum relevant to industry needs. I’ve been recognized as a McAfee next generation leader and regularly speak at universities and STEM events to inspire the next generation of security talent.
Eoin Carroll’s Current Industry Toyota North America
Eoin
Carroll’s Prior Industry
Xilinx
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Intel
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Boston Scientific
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Mcafee
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Qualcomm
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Ieee
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Cyber
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Toyota North America
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Work Experience

Toyota North America
Principal Product Cybersecurity Engineer
Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mcafee
Principal Engineer, Advanced Threat Research
Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Cyber
Cyber Ireland Technical Leader
Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Cyber
Cyber Ireland member
Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Ieee
IEEE Ireland member
Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mcafee
Sr. Vulnerability Researcher, Advanced Threat Research
Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Mcafee
Endpoint Product Security Architect Lead
Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Staff IT Security Engineer
Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Mcafee
Software Security Engineer
Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Boston Scientific
Electrical Test and Software Development Engineer
Fri Jun 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Wafer Sort Test Development Engineer
Wed Jun 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Product Test Engineer
Tue Aug 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)