
Gaurav Hamde
Hi all, I am Gaurav. I have completed my master's from San Jose State University in Electrical Engineering specialising... | San Francisco Bay Area, San Francisco Bay Area, United States
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Gaurav Hamde’s Emails gh****@nv****.com
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Gaurav Hamde’s Location San Francisco Bay Area, San Francisco Bay Area, United States
Gaurav Hamde’s Expertise Hi all, I am Gaurav. I have completed my master's from San Jose State University in Electrical Engineering specialising in VLSI (Digital Systems and Logic Design). Currently, I am working as an Automotive SQA Engineer at NVIDIA. Work Experience:- •Automotive SQA Engineer at NVIDIA Corp. Santa Clara,CA. (Sept'17-Present) Jr. ASIC Design Engineering Intern at SSR Labs Inc. San Jose, CA (Feb'17-Sept'17) •Instructional Student Assistant at Electrical Engineering Department San Jose State University (Sept'16-Dec'16) •Instrumentation Engineer at IPAC Automation Pvt. Ltd. Pune, India (Jul'14-Nov'14) •Internship at NICE Consultancy Mumbai, India (Aug'12-May'13) Technical Skills:- •Proficient in Verilog •Programming Skills: - C, Python, Assembly, MatLab. •Proficient in RTL Design, RTL Simulation, RTL Synthesis, Static Timing Analysis (STA), Place and Route, Design for Testability (DFT SCAN, BIST). •Good understanding of Computer Architecture MIPS/RISC processor architecture, Cache Organization, Virtual memory. •Verification: - System Verilog Assertions, Test bench development, Functional Coverage. •BUS protocols: - AMBA AHB, APB, AXI, UART. •Tools: - VCS Synopsys, Synopsys (Design Vision, Design Compiler, IC Compiler), Cadence Virtuoso, Cadence Spectre, GTKWave, Xilinx (Vivado, ISE), Altera (Quartus II, Prime Lite, ModelSim), AutoCAD. •Hardware: - Altera DE-1, Altera DE-1 Cyclone V SoC, Altera DE-0 nano SoC, Tiny6410 ARM11. •Analog: - Cadence 6.1, ADC-TDC, PLL modelling. •Operating Systems: - UNIX, Linux, Mac OS, Windows.
Gaurav Hamde’s Current Industry Nvidia
Gaurav
Hamde’s Prior Industry
Nice Consultancy
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Ipac Automation
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San Jose State University
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Nvidia
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Work Experience

Nvidia
Senior SWQA Engineer
Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Nvidia
Automotive SQA Engineer
Fri Sep 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
San Jose State University
Instructional Student Assistant
Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Ipac Automation
Instrumentation Engineer
Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Nov 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Nice Consultancy
Internship
Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)