
Gaurav Srivastava
Currently working with Intel Corporation as SoC Design Engineer working on compensation block and DDR5 controller. Prior to... | Bothell, Washington, United States
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Gaurav Srivastava’s Emails ga****@sy****.com
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Gaurav Srivastava’s Location Bothell, Washington, United States
Gaurav Srivastava’s Expertise Currently working with Intel Corporation as SoC Design Engineer working on compensation block and DDR5 controller. Prior to that worked with Synopsys as Electrical Design Engineer working on Non Volatile Memory design. Earlier worked with Cypress Semiconductors as a Staff Electrical Design Engineer on Programmable System on Chip. Completed Master's in Electrical and Computer Engineering at Carnegie Mellon University. Graduated in May, 2016. Focus areas in Masters were Computer Systems, Parallel Computing, and Computer Architecture. Have 3.5 years of experience in Oracle Corporation as Application Developer in SQL, PL/SQL (2011-2014). Job included design and enhancement of features in Oracle Financial Suites (Account Receivables). Also was lead on the Apex project involving automating common errors in the Account Receivables systems. Prior to that completed Integrated Masters in Applied Physics in IIT-BHU. Participated in various technical competition including Image Processing, Autonomous robotics, Line Follower.
Gaurav Srivastava’s Current Industry Intel
Gaurav
Srivastava’s Prior Industry
Bhabha Atomic Research Centre
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Gallium Arsenide Enabling Technology Centre
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Oracle
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Cypress Semiconductor
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Synopsys
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Intel
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Work Experience

Intel
Digital Designer
Wed Dec 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
ASIC Digital Design Engineer, Senior I
Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Cypress Semiconductor
Staff Electrical Design Engineer
Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Cypress Semiconductor
Senior Electrical Design Engineer
Fri Jul 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Oracle
Application Engineer
Wed Jun 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Dec 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Gallium Arsenide Enabling Technology Centre
Research Intern
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Bhabha Atomic Research Centre
Research Intern
Tue Apr 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)