Glen Wu

Glen Wu

• APU/GPU Full Chip Floorplan • Physical design from RTL to GDS. • TCL/Perl Scripts • Low power design and Power analysis | Canada

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Work Experience

Intel

SoC Design Engineer

Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Amd

Senior Member Of Technical Staff

Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Member Of Technical Staff

Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Senior Silicon Design Engineer

Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Silicon Design Engineer 2

Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Stmicroelectronics

Physical Design Engineer

Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Cisco Systems

ASIC Design Verification Intern

Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Cisco Systems

ASIC Physical Design Intern

Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

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