
Harish Lalithkumar
3 + Yrs of Experience in SOC Pre- Si Validation. Knowledge of eMMC 5.0/SDIO 3.0 controller architecture and design. eMMC5.0... | 9231 Southwest Chopin Lane, Portland, United States
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Harish Lalithkumar’s Location 9231 Southwest Chopin Lane, Portland, United States
Harish Lalithkumar’s Expertise 3 + Yrs of Experience in SOC Pre- Si Validation. Knowledge of eMMC 5.0/SDIO 3.0 controller architecture and design. eMMC5.0 Jedec Protocol, SD/SDIO 3.0 protocol. Experience in OVM/Saola Test Bench Environment. Experience in Writing Test Plan and providing review. Experience in Unit Level Validation of IP which includes writing tests, assertions and coverage based on System Verilog. Debugging Skills in VCS and ACE tools. Experience in GLS for PHY blocks. Experience in SOC GLS and Timing Simulations.
Harish Lalithkumar’s Current Industry Intel
Harish
Lalithkumar’s Prior Industry
Infosys
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Intel
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Work Experience

Intel
Design Verification Lead
Tue Sep 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Design Verification Engineer
Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Pre Silicon Validation Engineer
Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Software Intern
Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Infosys
Software Engineer
Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)