Harish Lalithkumar

Harish Lalithkumar

3 + Yrs of Experience in SOC Pre- Si Validation. Knowledge of eMMC 5.0/SDIO 3.0 controller architecture and design. eMMC5.0... | 9231 Southwest Chopin Lane, Portland, United States

*50 free lookup(s) per month.

No credit card required.

Harish Lalithkumar’s Emails

Harish Lalithkumar’s Phone Numbers

Social Media

Harish Lalithkumar’s Location

Harish Lalithkumar’s Expertise

Harish Lalithkumar’s Current Industry

Harish Lalithkumar’s Prior Industry

Not the Harish Lalithkumar you were looking for?

Find accurate emails & phone numbers for over 700M professionals.

Work Experience

Intel

Design Verification Lead

Tue Sep 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Design Verification Engineer

Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Pre Silicon Validation Engineer

Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Software Intern

Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)

Infosys

Software Engineer

Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

No languages available.