
Hemant Jain
Proven senior level design engineer expertise with more than 20 years of experience in the development of high... | Bengaluru, Karnataka, India
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Hemant Jain’s Location Bengaluru, Karnataka, India
Hemant Jain’s Expertise Proven senior level design engineer expertise with more than 20 years of experience in the development of high quality, mass market products in the processor , chipsets and Consumer Electronics industry. My goal is to seek a responsible and challenging position in a technology driven company and use my experience to lead a team of world class engineering professionals who can deliver technology and products of the future. Achievements: * Leading/working with geographical distributed teams on the ASIC development activities. * Responsible for the Tape-out of the products generating revenue of 1billion dollar plus * Contributed significantly into methodology for the product design. Specialties: * Immense experience in all stages of the physical design of processor graphics, chipsets and SOCs * Expertise in the various process technologies ranging from 250nm to 14nm * Expertise in the industry standard tools from Synopsis, cadence,mentor, etc. * Overall experience of full design and development from RTL coding, RTL verifcation, Analog circuit design and Physical design. * In depth knowledge gained in the Floorplan, Power Delivery network, Power gating and Integration of Complex Large Design like Chipsets, Graphics.
Hemant Jain’s Current Industry Intel
Hemant
Jain’s Prior Industry
Genesis Microchip Sage
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Intel
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Work Experience

Intel
Principal Engineer
Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Floorplan And Integration Lead
Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Technical Lead
Wed Apr 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Lead Graphics Design Engineer
Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Component Design Engineer
Sat Apr 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Genesis Microchip Sage
Member Of Technical Staff Physical Design
Tue Jul 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Genesis Microchip Sage
Member Of Technical Staff Analog Design
Wed Aug 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Genesis Microchip Sage
Member Of Technical Staff Front End Design
Tue Aug 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)