Hsinho Wu

Hsinho Wu

* Over 20 years experience in research, development, product definition and customer engagement * Specialized in signal integrity modeling... | San Jose, California, United States

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Work Experience

Altera

Principal Engineer

Mon Jan 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Principal Engineer, Design Engineering Group

Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Design Engineer at Programmable Solutions Group

Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Altera

Principal Design Engineer

Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

National Semiconductor

Principle Design Engineer

Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

National Semiconductor

Principle Systems Development Engineer

Tue Jul 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

National Semiconductor

Staff Systems Development Engineer

Tue Feb 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)

National Semiconductor

Staff Systems Development Engineer

Mon Mar 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)

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