
Hsinho Wu
* Over 20 years experience in research, development, product definition and customer engagement * Specialized in signal integrity modeling... | San Jose, California, United States
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Hsinho Wu’s Emails hs****@in****.com
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Hsinho Wu’s Location San Jose, California, United States
Hsinho Wu’s Expertise * Over 20 years experience in research, development, product definition and customer engagement * Specialized in signal integrity modeling and simulation for high-speed mixed-signal communication links * SerDes and high-speed link simulation platform supporting IBIS-AMI models: Advanced Link Analyzer * IBIS-AMI model generation * IEEE 802.3 Ethernet (10M/100M/1G/10G/25G/40G/53G/106G), OIF-CEI (28G/56G/112G), JESD204, PCI-Express (8G/16G/32G/64G), HDMI/DVI, SATA/SAS, SMPTE, and proprietary links * C/C++/C#, Microsoft .NET, Perl, GUI, API, Intel MKL * Tools: Matlab, KeySight ADS, HyperLynx, Mathworks/SiSoft QCD Specialties: System Modeling, Signal Integrity, High-Speed Communications, Channel Equalization, Statistical Signal Processing, Channel Modeling, Optical Communication, Computer Architectures, IEEE 802.3 Ethernet, HDMI/DVI, SATA/SAS, SMPTE, Matlab, Agilent ADS, C/C++, IBIS, IBIS-AMI
Hsinho Wu’s Current Industry Altera
Hsinho
Wu’s Prior Industry
National Semiconductor
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Altera
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Intel
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Work Experience

Altera
Principal Engineer
Mon Jan 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Principal Engineer, Design Engineering Group
Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Design Engineer at Programmable Solutions Group
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Altera
Principal Design Engineer
Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
National Semiconductor
Principle Design Engineer
Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
National Semiconductor
Principle Systems Development Engineer
Tue Jul 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
National Semiconductor
Staff Systems Development Engineer
Tue Feb 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
National Semiconductor
Staff Systems Development Engineer
Mon Mar 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)