
James Lin
* Passionate in tackling the challenges in LC/RO PLL design, high speed clock dividers and clock path jitter... | Richmond Hill, Ontario, Canada
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James Lin’s Emails ja****@sy****.com
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James Lin’s Location Richmond Hill, Ontario, Canada
James Lin’s Expertise * Passionate in tackling the challenges in LC/RO PLL design, high speed clock dividers and clock path jitter optimizations * Building SerDes PLL's in the latest technology nodes
James Lin’s Current Industry Synopsys
James
Lin’s Prior Industry
Synopsys
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Fresco Microchip
|
Amd
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Work Experience

Synopsys
Sr Manager, Analog and Mixed Signal Design
Wed Feb 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Manager II, Analog Design and Mixed Signal Design
Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Staff Analog Designer
Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
MTS Analog Designer
Mon Mar 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Fresco Microchip
Analog Designer
Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
R&D Engineer
Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)