
Jeff Meyer
40 years of experience in analog RF IC design, microwave design, digital hardware/firmware, and EDA software... | Santa Rosa, California, United States
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Jeff Meyer’s Emails jm****@so****.net
Jeff Meyer’s Phone Numbers No phone number available.
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Jeff Meyer’s Location Santa Rosa, California, United States
Jeff Meyer’s Expertise 40 years of experience in analog RF IC design, microwave design, digital hardware/firmware, and EDA software development including project management and product planning. Expertise in analog and high speed, high frequency simulation algorithms. 20 years of analog and microwave design experience designing both discrete and integrated circuits. Experience in modern digital design methodologies using Verilog HDL and logic synthesis tools. Over 20 years of experience in software and hardware project management. Specialties: Engineering experience in both hardware and software. Experience in design and management. Hands on experience in High speed Digital design as well as analog & RF design. GaAs pHEMT IC design experience. A Linux enthusiast as a hobby. Over 20 years of management experience at different employers.
Jeff Meyer’s Current Industry Gjobs
Jeff
Meyer’s Prior Industry
Hewlett Packard
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Cisco Systems
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Centellax
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Symmetricom
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Microsemi
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Gjobs
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Work Experience

Gjobs
Retired
Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Microsemi
Systems Architect
Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Centellax
CT0
Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Centellax
Strategic Product Manager
Fri Feb 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Symmetricom
Director of Hardware Engineering
Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Centellax
Director of Engineering
Sat Jun 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Cisco Systems
Technical Leader
Mon May 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Hewlett Packard
R&D Section Manager
Thu Jun 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)
Hewlett Packard
R&D Engineer & Project Manager
Thu Jun 01 1978 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon May 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time)