
Jeff Sabuda
CAREER PROFILE With 25+ years in semiconductor design, I'm dedicated to pushing the boundaries of technology. At Triple Crown... | Austin, Texas, United States
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Jeff Sabuda’s Location Austin, Texas, United States
Jeff Sabuda’s Expertise CAREER PROFILE With 25+ years in semiconductor design, I'm dedicated to pushing the boundaries of technology. At Triple Crown Consulting Engineering Services, I lead a talented team in delivering top-tier silicon solutions across industries. My focus on quality, performance, and innovation ensures we exceed client expectations. From project inception to execution, I foster collaboration and drive strategic vision, steering us towards future success. Let's connect to explore how we can drive silicon innovation together! ENGINEERING HIGHLIGHTS • Experienced engineer with 25+ years of experience in design, implementation and verification of ASIC and FPGA products from conception through validation. • Extensive project lead, management, and resource development experience. • Full ASIC flow experience with many tape outs. • Complex ASIC SOCs and FPGA designs, chip verification, and FPGA prototyping. • Extensive FPGA design and emulation experience using Altera StratixIV, StratixV and ArriaV devices, Xilinx Virtex 7 and Ultrascale+ devices. • Deep knowledge in architecture and micro-architecture at the chip and module level to meet functional requirements of the complete system and create design specification documents. • Extensive knowledge in FPGA and ASIC design methodology, environment set up, and Verilog simulation. • Extensive knowledge on verification methodology, environment architecture, test plan generation, test bench automation, ASIC simulators, ASIC test execution, debugging, assertions and coverage analysis. • Deep knowledge of networking, peripheral, DoD comm, wireless, SDR and security and protocols. • Comprehensive knowledge of the ARM Core, bus architectures and system bus protocols.. • Evaluated and selected ASIC vendors and FPGA packages. • Script creation and modification using Perl, Python and Tcl. TECHNICAL SKILLS • SystemVerilog RTL Design • Front-End Logic Synthesis using Synopsys DC, Cadence RC compiler and Virtuoso • Static Timing Analysis using Synopsys PrimeTime and TimeQuest Timing Analyzer • HDL Simulators Synopsys VCS and Mentor Graphics Questa • Low Power Design and Optimization, UPF • Logic Equivalency Checking using Formality and LEC • Linting using Spyglass • Clock domain crossing design and verification using 0-in • DFT, Tetramax for ATPG, Tessent for MBist and Boundary Scan • MATLAB/Simulink • FPGA design and verification using Altera’s QuartusII and Signal Tap, and Xilinx’s ISE, Vivado, & Chip Scope.
Jeff Sabuda’s Current Industry Triple Crown
Jeff
Sabuda’s Prior Industry
Fujitsu Network Communications
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Nortel Networks
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Calix
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Smsc
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Mayflower Communications
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Freescale Semiconductor
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Anue Systems
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Tezzaron Semiconductor
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Ulthera
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Global Foundries
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Teledyne Lecroy
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Microchip Technology
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Triple Crown
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Work Experience

Triple Crown
Chief of Silicon
Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Microchip Technology
Manager and Lead, Digital Design Engineering
Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Feb 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Teledyne Lecroy
Senior Technical Staff Design Engineer
Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Global Foundries
ASIC Design Engineer
Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Ulthera
FPGA Design and Verification Engineer
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Tezzaron Semiconductor
Senior Member of Technical Staff
Mon Dec 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Anue Systems
Principal Design Engineer at Anue Systems
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Smsc
ASIC Design Engineer
Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Freescale Semiconductor
FPGA Design Engineer
Wed Dec 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Mayflower Communications
FPGA Design Engineer
Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Smsc
ASIC Design Engineer
Tue Apr 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Calix
Principal ASIC Design Engineer
Sun Oct 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Nortel Networks
Senior ASIC Design Engineer
Mon Apr 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)
Fujitsu Network Communications
ASIC Verification Engineer
Thu Jul 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time)