Jeff Sabuda

Jeff Sabuda

CAREER PROFILE With 25+ years in semiconductor design, I'm dedicated to pushing the boundaries of technology. At Triple Crown... | Austin, Texas, United States

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Work Experience

Triple Crown

Chief of Silicon

Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Microchip Technology

Manager and Lead, Digital Design Engineering

Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Feb 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)

Teledyne Lecroy

Senior Technical Staff Design Engineer

Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Global Foundries

ASIC Design Engineer

Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Ulthera

FPGA Design and Verification Engineer

Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Tezzaron Semiconductor

Senior Member of Technical Staff

Mon Dec 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Anue Systems

Principal Design Engineer at Anue Systems

Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Smsc

ASIC Design Engineer

Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)

Freescale Semiconductor

FPGA Design Engineer

Wed Dec 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)

Mayflower Communications

FPGA Design Engineer

Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)

Smsc

ASIC Design Engineer

Tue Apr 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)

Calix

Principal ASIC Design Engineer

Sun Oct 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)

Nortel Networks

Senior ASIC Design Engineer

Mon Apr 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)

Fujitsu Network Communications

ASIC Verification Engineer

Thu Jul 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time)

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