
Jinwen Xi
-High performance NPU architecture and micro-architecture for AI training and inference. -15+ years’ hands on experience in micro-architecture... | 1628 South Mary Avenue, Sunnyvale, United States
*50 free lookup(s) per month.
No credit card required.
Jinwen Xi’s Emails jx****@ca****.com
Jinwen Xi’s Phone Numbers No phone number available.
Social Media
Jinwen Xi’s Location 1628 South Mary Avenue, Sunnyvale, United States
Jinwen Xi’s Expertise -High performance NPU architecture and micro-architecture for AI training and inference. -15+ years’ hands on experience in micro-architecture definition, exploration and implementation of high-performance/low-power DSP targeting communication/networking/video/image applications. -Full-flow ASIC design including micro-architecture, RTL implementation, verification, logic synthesis, timing closure, LEC, and silicon debug. Successfully taped-out 5 chips since 2006. -Deep understanding of embedded processor architecture with hands-on experience on ISA definition. -Trade-off analysis for performance/power/area during the early stages of “algorithm to silicon” process and select the most appropriate architecture/implementation to meet the PPA goals. -Digital filter design for communication DSP: FIR, IIR, CIC, sample-rate conversion, etc., and their high-performance/low-power derivatives. -Comprehensive knowledge on AI/machine learning: linear/logistic regression, classification, CNN, RNN/LSTM. etc. Implemented some ML algorithms with Octave/Python(NumPy). Took certified training from Stanford University/Coursera. -Management of contractors to perform the RTL design, verification, and backend implementation. Task analysis and partitioning, progress tracking and milestone review. Took the leadership training from Tulip Management. -Verilog/VHDL, RTL Compiler/Genus, Conformal LEC, Perl, Python/NumPy, tcl, Matlab/Octave, C/C++. -Working knowledge of advanced AI/ML programming frameworks: TensorFlow, Keras
Jinwen Xi’s Current Industry Microsoft
Jinwen
Xi’s Prior Industry
Microsoft
|
Cadence Design Systems
|
Intel
|
Michigan State University
|
Texas Instruments
|
Appliedmicro
|
Xingtera
|
Tensilica
Not the Jinwen Xi you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Microsoft
Principal Ai Hardware Architect
— Present
Cadence Design Systems
Shuiguohu High School
— Present
Intel
Product Engineer
Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time)
Michigan State University
Embedded Processor Architect
— Present
Texas Instruments
Digital System Architect And Designer
— Present
Cadence Design Systems
Senior Principal Design Engineer
— Present
Microsoft
Principal Ai Hardware Architect
— Present
Appliedmicro
Principal Design Engineer
— Present
Xingtera
Principal Design Engineer And Design Lead
— Present
Tensilica
Senior Principal Design Engineer
— Present