
Joey Moriguchi
Seasoned and recognized Physical Designer Engineer with a strong talent to take on complex problems, and document the... | Folsom, California, United States
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Joey Moriguchi’s Location Folsom, California, United States
Joey Moriguchi’s Expertise Seasoned and recognized Physical Designer Engineer with a strong talent to take on complex problems, and document the problem-solving process. Possess 25+ years combined of experience in the Circuit Design business, with 16+ years in the mixed-signal IP, with an emphasis on Family IP Integration, ESD design and validation, and analog/mixed-signal block/cell layout design. Have experience in both Intel and TSMC sub-micron processes. Have experience in design and debug tools – including Cadence Virtuoso, Siemens Calibre and Synopsis ICV verification, RedHawk/Totem Power RV, Ansys/Apache ESD validation tools (PathFinder), Siemens Calibre PERC_ESD, and Synopsis Fusion Compiler.
Joey Moriguchi’s Current Industry Intel
Joey
Moriguchi’s Prior Industry
Intel
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Work Experience

Intel
Senior Mask Designer - Analog/Mixed Signal
Sat Sep 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Mask Designer (Digital)
Fri Sep 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Mask Designer - Analog/Mixed Signal
— Present