John Tseng

John Tseng

Small Company and Large Company Experience with multiple tape outs in leading edge process nodes. Goals: Building infrastructure and... | Redwood City, California, United States

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Work Experience

Esperanto Technologies

Sr CAD/PD Lead

Sat Apr 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Cerebras Systems

Senior Member of Technical Staff

Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Technical Director, VLSI

Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Director, VLSI Methdology

Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Altera

Sr Methodology Engineer

Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Sr Methodology Engineer

Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Avago Technologies

Sr. Engineering Manager

Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Lsi An Avago Technologies

Sr. Engineering Manager

Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Sandforce

Engineering Manager, Physical Design

Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Seagate Technology

Engineer

Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Sandforce

Senior Principle Engineer

Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Amcc

Senior Principle Engineer

Mon Oct 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)

Montalvo Systems

Senior Methodology Lead

Mon Aug 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)

Pasemi

ASIC CAD Manager

Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)

Pa Semi

ASIC CAD Manager

Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)

Pasemi

Senior Principle Engineer

Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)

Raza Microelectronics

Director of Physical Design

Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)

Raza Foundries

Engineer In Residence

Thu Nov 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)

Nishan Systems

Senior Engineer

Sat Apr 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Senior Engineer

Sun Oct 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)

Nexgen

Design Engineer

Mon May 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

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