Karthikeya Palepu

Karthikeya Palepu

ASIC Verification Engineer with focus on Graphics, Server and Client Memory controller verification. | San Jose, California, United States

*50 free lookup(s) per month.

No credit card required.

Karthikeya Palepu’s Emails

Karthikeya Palepu’s Phone Numbers

Social Media

Karthikeya Palepu’s Location

Karthikeya Palepu’s Expertise

Karthikeya Palepu’s Current Industry

Karthikeya Palepu’s Prior Industry

Not the Karthikeya Palepu you were looking for?

Find accurate emails & phone numbers for over 700M professionals.

Work Experience

Amd

SMTS Silicon Design Engineer

Mon Jul 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Amd

MTS Silicon Design Engineer

Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Sr. Silicon Design Engineer

Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Sr. ASIC/Layout Engineer

Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Micron Technology

Asic Verification Engineer

Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Covidien

Intern-R&D Electrical Engineering.

Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

No languages available.