
Karthikeya Palepu
ASIC Verification Engineer with focus on Graphics, Server and Client Memory controller verification. | San Jose, California, United States
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Karthikeya Palepu’s Emails ka****@am****.com
Karthikeya Palepu’s Phone Numbers No phone number available.
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Karthikeya Palepu’s Location San Jose, California, United States
Karthikeya Palepu’s Expertise ASIC Verification Engineer with focus on Graphics, Server and Client Memory controller verification.
Karthikeya Palepu’s Current Industry Amd
Karthikeya
Palepu’s Prior Industry
Covidien
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Micron Technology
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Amd
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Work Experience

Amd
SMTS Silicon Design Engineer
Mon Jul 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Amd
MTS Silicon Design Engineer
Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
Sr. Silicon Design Engineer
Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
Sr. ASIC/Layout Engineer
Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Micron Technology
Asic Verification Engineer
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Covidien
Intern-R&D Electrical Engineering.
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)