
Kevin Allen
A broad-span silicon design engineer with traditional strengths and experience in front-end design and more recent experience in... | Broadcom, 220 Bristol Business Park Coldharbour Lane, United Kingdom
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Kevin Allen’s Emails ke****@br****.com
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Kevin Allen’s Location Broadcom, 220 Bristol Business Park Coldharbour Lane, United Kingdom
Kevin Allen’s Expertise A broad-span silicon design engineer with traditional strengths and experience in front-end design and more recent experience in complex semi-custom physical design. Historically an engineer with significant RTL coding and verification experience for ASIC and FPGA, now focusing more on leading complex physical design (synthesis, place-and-route and complex STA), both flow development and implementation using those flows. Specialties: Verilog, Magma Blast Fusion, Synopsys DC/DC-T/DFT-C, PrimeTime
Kevin Allen’s Current Industry Broadcom
Kevin
Allen’s Prior Industry
Broadcom
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Icl
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Fujitsu Telecommunications Europe
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Ftel
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Phyworks
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Designabstraction
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Clearspeed Technology
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Dialog Semiconductor
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Nvidia
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Work Experience

Broadcom
Principal Ic Design Engineer
Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Nvidia
Silicon Asic Design Engineer
Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Dialog Semiconductor
Principal Digital Design Engineer
Wed Jul 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Clearspeed Technology
Silicon Design Engineer
Sun Aug 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Designabstraction
Asic Engineer
Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Aug 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Phyworks
Principal Engineer
Wed May 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Nov 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Ftel
Principal Asic Engineer
Tue Feb 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Fujitsu Telecommunications Europe
Principal Asic Engineer
Tue Feb 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Fujitsu Telecommunications Europe
Principal Asic Engineer
Sat Jan 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Icl
Asic Design Engineer
Sat Aug 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
Principal IC Design Engineer
— Present