Kiran

FAQ About Kiran

• What is Kiran 's address?

  Kiran is located at
  United States

• What is Kiran 's job title?

  Kiran is a
  Currently working as AMS integration timing engineer at Apple Worked as FullChip (SOC) STA lead at Google leading DFT and functional timing for test-chips and product-chips. Worked at Apple for 2 years as Front End Synthesis STA methodology engineer with strong experience in Syn constraints, STA Signoff, synthesis timing optimization, DSLG scaling and spice simulations to generate derates. Worked at Intel for 4.5 years in BackEnd PD/STA Methodology/Execution with strong experience in VF curve, PDN (IR) based STA, PV2Si debug using Spice, Vmin analysis for 8-T SRAM, stdcell library characterization, STA features: CCS Dx/RX modeling, AWP, POCV/LVF/Moments, XPV using LPPI/SMVA, CAD Physical Design methodology/execution (synthesis to post_Route timing/routing convergence). Summary: -Strong experience in VF curve analysis to determine the PVT corner points by analyzing the Vmin, Aging, PDN (IR-drop) aspects, process/device variations (systematic/random), sigma convergence points and reliability using SPICE modeling with different work-load model benchmarks to analyze its impact on overall PPA of design. -Strong experience in SOC STA (DFT/Func) constraints, convergence, eco-sign off by closely working with architecture. Also expert in timing/power ECO techniques at SOC level with flat, hierarchical and stub timing models. -Contributed for improvement of backend methodology in Timing/Layout closures by developing a tool (python/tcl) to catch issues before the execution phase to save the project turnaround time. -Worked on several low-power techniques such as mbit optimization, clock gating structures, leakage reduction at block level. -Experience in spice to model Die-Die (3-D IC package) (static/crosstalk) noise analysis to model in STA at Die level. Awarded division level and department level Recognition for debug on PV2Silicon timing miscorrelation for 10nm process at Intel. Awarded department level recognition for closing the STA for 3nm test-chip at Google. Awarded Qualstar for converging test-chip block in 14nm at Qualcomm during internship. Masters in Electrical Engineering at University of Texas at Dallas, USA with specialization in VLSI Digital systems. Apple

• What industry does Kiran currently work in?

  Kiran currently works in the
  Apple

• What is Kiran 's area of expertise?

  Kiran specializes in
  Currently working as AMS integration timing engineer at Apple Worked as FullChip (SOC) STA lead at Google leading DFT and functional timing for test-chips and product-chips. Worked at Apple for 2 years as Front End Synthesis STA methodology engineer with strong experience in Syn constraints, STA Signoff, synthesis timing optimization, DSLG scaling and spice simulations to generate derates. Worked at Intel for 4.5 years in BackEnd PD/STA Methodology/Execution with strong experience in VF curve, PDN (IR) based STA, PV2Si debug using Spice, Vmin analysis for 8-T SRAM, stdcell library characterization, STA features: CCS Dx/RX modeling, AWP, POCV/LVF/Moments, XPV using LPPI/SMVA, CAD Physical Design methodology/execution (synthesis to post_Route timing/routing convergence). Summary: -Strong experience in VF curve analysis to determine the PVT corner points by analyzing the Vmin, Aging, PDN (IR-drop) aspects, process/device variations (systematic/random), sigma convergence points and reliability using SPICE modeling with different work-load model benchmarks to analyze its impact on overall PPA of design. -Strong experience in SOC STA (DFT/Func) constraints, convergence, eco-sign off by closely working with architecture. Also expert in timing/power ECO techniques at SOC level with flat, hierarchical and stub timing models. -Contributed for improvement of backend methodology in Timing/Layout closures by developing a tool (python/tcl) to catch issues before the execution phase to save the project turnaround time. -Worked on several low-power techniques such as mbit optimization, clock gating structures, leakage reduction at block level. -Experience in spice to model Die-Die (3-D IC package) (static/crosstalk) noise analysis to model in STA at Die level. Awarded division level and department level Recognition for debug on PV2Silicon timing miscorrelation for 10nm process at Intel. Awarded department level recognition for closing the STA for 3nm test-chip at Google. Awarded Qualstar for converging test-chip block in 14nm at Qualcomm during internship. Masters in Electrical Engineering at University of Texas at Dallas, USA with specialization in VLSI Digital systems.

• Which languages does Kiran speak? 

  Kiran speaks the following languages:
  No languages available.

• Which industries has Kiran previously worked in?   

  Kiran has prior experience in the following industries:
  Google , Apple , Intel , Intel , Qualcomm , University Of Texas At Dallas , Tata Consultancy Services , Ecil , Bharat Heavy Electricals

• What is Kiran ’s work experience?  

  Kiran has the following professional experience:
  Apple , Google , Apple , Intel , Intel , Qualcomm , University Of Texas At Dallas , Tata Consultancy Services , Ecil , Bharat Heavy Electricals .

• How can I find Kiran on LinkedIn?  

  You can view Kiran ’s
  LinkedIn profile at LinkedIn URL.

• What are Kiran ’s work email addresses?  

  Kiran ’s work email addresses are
  [email protected] .

• What company does Kiran work for?  

  Kiran works at
  Apple