
Kotapati Ramalingareddy
As a physical design Engineer, Having very good experience in working on GPU, Automotive at 45nm ,32 nm... | Bothell, Washington, United States
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Kotapati Ramalingareddy’s Emails ra****@in****.com
Kotapati Ramalingareddy’s Phone Numbers 1408956****
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Kotapati Ramalingareddy’s Location Bothell, Washington, United States
Kotapati Ramalingareddy’s Expertise As a physical design Engineer, Having very good experience in working on GPU, Automotive at 45nm ,32 nm and 28nm, 16ff and 7nm technologies. Experienced in Synthesis, floorplaning, placement ,clock tree synthesis, timing closure, Ecos, DRC and LVS block level and chip level closure. Strong knowledge in signal integrity issues such cross-talk, EM and IR drop. Working knowledge of low power methodologies and impact on overall design goals. Experience in main P&R tools from Synopsys(ICC), Cadence(SOCE), ATOP TECH. Knowledge of post layout physical verification and DFM rules. - Working knowledge of Verilog - Solid understanding of UNIX/LINUX - Experienced in scripting – TCL, PERL, Shell Specialties Excellent debug and analytical skills to resolve urgent issues related to physical design. Having good experience in leading the projects as a project Lead from synthesis to physical design. closure. Strong communication and interpersonal skills to work closely with various teams across the globe. Have Working knowledge of Fusion Compiler, Innovus , SocEncounter, ICC & ICC2, ATOP TECH, PrimeTime, DC, Verilog, Sierra Pinacle, Redhawk and Calibre.
Kotapati Ramalingareddy’s Current Industry Infineon Technologies
Kotapati
Ramalingareddy’s Prior Industry
Soctronics
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Amd
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Smartplay Technologies An Aricent
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Infineon Technologies
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Work Experience

Infineon Technologies
Principal Engineer
Sat Apr 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Infineon Technologies
Senior Staff Design Engineer
Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Smartplay Technologies An Aricent
Senior Technical Lead
Sat Oct 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Smartplay Technologies An Aricent
Technical Lead
Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
Senior Design Engineer
Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Soctronics
Senior Design Engineer
Mon Sep 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)