
Kumar Raghavendra
Accomplished Physical Design Engineer with 6+ years of experience in the semiconductor industry, specializing in various aspects of... | Bengaluru, Karnataka, India
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Kumar Raghavendra’s Emails kr****@in****.com
Kumar Raghavendra’s Phone Numbers 91404392****
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Kumar Raghavendra’s Location Bengaluru, Karnataka, India
Kumar Raghavendra’s Expertise Accomplished Physical Design Engineer with 6+ years of experience in the semiconductor industry, specializing in various aspects of physical design from floorplanning to GDS. Track record in showcasing exceptional performance, expertise in physical design, static timing analysis, place & route, ECO implementation, LEC, physical verification, flow integration, signal EM/IR analysis, and proficiency in TCL scripting for efficient design processes and debugging. Proven leadership abilities in team management, technical guidance, and complex issue resolution. Committed to driving innovation, optimizing performance, and exceeding client expectations. Proven track record of achieving exceptional results in designing high-complexity projects with instance counts exceeding 4 million, across various cutting-edge technology nodes ranging from 28nm to 7nm. Proficiently handled clock frequencies surpassing 1 GHz. Proficient in utilizing industry-leading tools such as ICC2, Fusion Compiler, Primetime, Innovus, Design Compiler, Calibre, StarRC, Formality, Conformal, and ICV to deliver exceptional results. .
Kumar Raghavendra’s Current Industry Cadence Design Systems
Kumar
Raghavendra’s Prior Industry
Vlsiguru Training Institute
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Dpiind
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Whizchip Design Technologies
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Soctronics
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Invecas
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Cadence Design Systems
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Work Experience

Cadence Design Systems
Principal Design Engineer
Mon Jul 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Invecas
Member of Technical Staff
Sat Apr 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Invecas
Senior Physical Design Engineer
Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Invecas
Engineer 2
Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Soctronics
Engineer 2
Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Whizchip Design Technologies
Engineer VLSI Design
Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Dpiind
Design Engineer 1
Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Vlsiguru Training Institute
Physical Design Engineer Trainee
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)