
Manikandan Subramanian
- 18+ years of hands-on experience in IC Design Verification, RTL design and silicon/FPGA bring up. - Strong DV... | Colorado Springs, Colorado Springs, United States
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Manikandan Subramanian’s Emails ms****@nv****.com
Manikandan Subramanian’s Phone Numbers No phone number available.
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Manikandan Subramanian’s Location Colorado Springs, Colorado Springs, United States
Manikandan Subramanian’s Expertise - 18+ years of hands-on experience in IC Design Verification, RTL design and silicon/FPGA bring up. - Strong DV experience at block/sub-system/SOC levels encompassing wide range of cores/protocols - Coherent interconnects/caches (CHI/ACE), DDR memory controllers (DDR3/4 RDIMM/LRDIMM), Flash, PCIe controllers (Gen4/5), storage(SAS/SATA). Extensive SOC/system level experience. - Strong blend of communication, analytical, technical and people skills. - Proven leadership qualities with track record in mentoring, growing and establishing DV teams.
Manikandan Subramanian’s Current Industry Nvidia
Manikandan
Subramanian’s Prior Industry
Lsi An Avago Technologies
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Lsi
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Broadcom
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Qualcomm
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Nvidia
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Work Experience

Nvidia
Verification Lead
Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Nvidia
Verification Lead
Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Sr Staff Engineering Manager
Thu Oct 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
Principal Design & Verification Engineer
Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
Staff Design Verification Engineer
Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi
Staff Design Verification Engineer
Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi An Avago Technologies
Ic Design Engineer
Sat Jul 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)