Manjunath G

Manjunath G

• 5+ years of experience in semiconductor domain with good knowledge of ASIC design flow and working for... | Santa Clara, California, United States

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Work Experience

Intel

DFT/ATPG Engineer

Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Validation Engineer

Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Emulation Engineer

Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Wright State University

Graduate Student

Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Coreel Technologies

Intern

Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

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