Manoj Badkas

Manoj Badkas

I have completed my Masters in Electrical Engineering specializing in Microelectronics from Hochschula Darmstadt, Germany in 2006. I am... | Bavaria, Bavaria, Germany

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Work Experience

Apple

Design Verification Engineer

Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel Deutschland

Design Verifiaction Engineer

Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Moschip Semiconductor

Staff Verification Engineer

Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Imagination Technologies

Leading Hardware Design Verifiaction Engineer

Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Xilinx

Design Verification Engineer

Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Seagate Technology

Design Verification Engineer

Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Lsi

Design Verification Engineer

Wed Jul 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Comit Systems

Hardware Engineer

Tue May 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)

Eubus

Hardware Engineer

Sun Oct 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)

Lipowsky Industrie Electronik

Hardware Engineer

Tue Mar 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)

Sasken Communication Technologies

M.Sc Thesis

Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)

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