
Manoj Badkas
I have completed my Masters in Electrical Engineering specializing in Microelectronics from Hochschula Darmstadt, Germany in 2006. I am... | Bavaria, Bavaria, Germany
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Manoj Badkas’s Emails ma****@se****.com
Manoj Badkas’s Phone Numbers No phone number available.
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Manoj Badkas’s Location Bavaria, Bavaria, Germany
Manoj Badkas’s Expertise I have completed my Masters in Electrical Engineering specializing in Microelectronics from Hochschula Darmstadt, Germany in 2006. I am working in semiconductor industry for 11+ years as a front-end digital verification engineer. I have experience in ASIC Verification using System Verilog and OVM/UVM, with hands on experience in Test bench and Test plan development, creating Verification environment and have experience in Assertion based verification as well. I have successfully worked on a few complex SOC/IP verification, Creating verification environment and SVC development. Presently I am working as a RF Verification Engineer with Intel Deutschland GmbH. Protocol Knowledge: - SAS/ SATA Controller/Expander - PICe - Ethernet XAUI. - SMBus, I2C. - SONET - AMBA AXI, AHB, APB Interfaces. Tools and Languages: - System Verilog (OVM & UVM methodologies), Verilog, VHDL. - Shell Scripting. - Waveform Debuggers (DVE, Verdi, SimVision).
Manoj Badkas’s Current Industry Apple
Manoj
Badkas’s Prior Industry
Sasken Communication Technologies
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Lipowsky Industrie Electronik
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Eubus
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Comit Systems
|
Lsi
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Seagate Technology
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Xilinx
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Imagination Technologies
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Moschip Semiconductor
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Intel Deutschland
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Apple
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Work Experience

Apple
Design Verification Engineer
Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel Deutschland
Design Verifiaction Engineer
Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Moschip Semiconductor
Staff Verification Engineer
Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Imagination Technologies
Leading Hardware Design Verifiaction Engineer
Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Design Verification Engineer
Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Seagate Technology
Design Verification Engineer
Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi
Design Verification Engineer
Wed Jul 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Comit Systems
Hardware Engineer
Tue May 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Eubus
Hardware Engineer
Sun Oct 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Lipowsky Industrie Electronik
Hardware Engineer
Tue Mar 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Sasken Communication Technologies
M.Sc Thesis
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)