
Manu Tandon
o Successfully delivered PCH PROD quality circuit design for test-chip, keeping tap of execution for on time PROD drop. o Successful... | Hillsboro, Oregon, United States
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Manu Tandon’s Emails ma****@in****.com
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Manu Tandon’s Location Hillsboro, Oregon, United States
Manu Tandon’s Expertise o Successfully delivered PCH PROD quality circuit design for test-chip, keeping tap of execution for on time PROD drop. o Successful PCH Silicon for PCH covering Signal Integrity & Power Integrity working with Platform team. o Groomed 10+ engineers in automation/methodology across site (Junior to Staff level), 8+ engineers in PCH circuit design team on circuit design (Junior to Senior level), Mentor to 8 engineers at Design Center. o Execution efficiency Leader for SoC team. o Design experience in Analog domain covering RX Buffer (RX), Differential Buffer (TX), Op-amps, Voltage Regulator, DLL, DAC and Class D Amplifier. o Methodology leadership and provided training for Analog domains covering Design Migration, Virtuoso ADE/ADEXL, AMS, Rel-Expert, Spectre/APS, Reliability Verification (Totem/Redhawk), Hercules/ICV for DRC & LVS, STAR-RC, QRC.
Manu Tandon’s Current Industry Intel
Manu
Tandon’s Prior Industry
Qualcore Logic
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Synopsys
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Intel
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Work Experience

Intel
Analog Engineering Manager
Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
SoC Design Manager / Technical Lead
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
SoC Design Engineer
Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Technical Leader/Manager-Design Methodology
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Lead Design Automation Engineer
Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Sr. Design Automation Engineer
Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
CAE
Tue Apr 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcore Logic
Member Technical Staff
Tue Aug 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)