Manu Tandon

Manu Tandon

o Successfully delivered PCH PROD quality circuit design for test-chip, keeping tap of execution for on time PROD drop. o Successful... | Hillsboro, Oregon, United States

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Work Experience

Intel

Analog Engineering Manager

Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

SoC Design Manager / Technical Lead

Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

SoC Design Engineer

Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Technical Leader/Manager-Design Methodology

Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Lead Design Automation Engineer

Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Sr. Design Automation Engineer

Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Synopsys

CAE

Tue Apr 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Qualcore Logic

Member Technical Staff

Tue Aug 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

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