
Marcus Pasquarella
Failure Analysis Engineer at National Semiconductor for 3 years. 15 years digital design experience in High speed... | Portland, Oregon, United States
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Marcus Pasquarella’s Emails ma****@in****.com
Marcus Pasquarella’s Phone Numbers No phone number available.
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Marcus Pasquarella’s Location Portland, Oregon, United States
Marcus Pasquarella’s Expertise Failure Analysis Engineer at National Semiconductor for 3 years. 15 years digital design experience in High speed serial communications and CPU team at Intel. Specialties: Digital IC design. Spec to RLS, high speed serial and CPU.
Marcus Pasquarella’s Current Industry Intel
Marcus
Pasquarella’s Prior Industry
Esi
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National Semiconductor
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Nserial
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Intel
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Work Experience

Intel
Mixed Signal Logic Design Engineering Manager
Thu Dec 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
SoC Design Engineer
Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Silicon Architecture Engineer & Engineering Manager
Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Silicon Architecture Engineer
Thu Feb 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Nserial
Engineer
Thu Jun 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)
National Semiconductor
Engineer
Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)
Esi
Intern
Mon Jan 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)