
Matthias Knoth
- power management of SOCs and CPU clusters power gating, DVFS, ultra low power micro architecture -... | San Francisco, California, United States
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Matthias Knoth’s Emails mk****@ap****.com
Matthias Knoth’s Phone Numbers No phone number available.
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Matthias Knoth’s Location San Francisco, California, United States
Matthias Knoth’s Expertise - power management of SOCs and CPU clusters power gating, DVFS, ultra low power micro architecture - CPU/ASIC thermal mitigation - microprocessor design fetch, pre-decode, branch target prefetch and issue units of multi threaded, single/super scalar microprocessors, bus interfaces, arithmetic pipelines, macro/micro architecture and implementation, debug infrastructure, sensor network instrumentation - large scale ASIC design through all stages - standard cell development -- circuit design, characterization, view generation, flow integration, quality assurance, benchmarking - XILINX, Lattice FPGA design - EDA tool development from HDL compilers, system integration tools to backend and GDSII manipulation tools. Tcl/TK - C++ integration Specialties: microprocessor design; power and performance management; full flow CPU and ASIC design; standard cell development; EDA tool development
Matthias Knoth’s Current Industry Apple
Matthias
Knoth’s Prior Industry
Infineon Technologies
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Quicksilver Technology
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Mips Technologies
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Apple
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Work Experience

Apple
Staff Architect
Wed Jun 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mips Technologies
Staff Design Engineer
Wed Sep 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Quicksilver Technology
Staff Hardware Design Engineer
Tue Apr 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Staff Hardware Design Engineer
Fri Mar 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)