
Mehul Patel
No headline available | Chandler, Arizona, United States
*50 free lookup(s) per month.
No credit card required.
Mehul Patel’s Emails me****@sy****.com
Mehul Patel’s Phone Numbers No phone number available.
Social Media
Mehul Patel’s Location Chandler, Arizona, United States
Mehul Patel’s Expertise Design verification Engineer
Mehul Patel’s Current Industry Cirrus Logic
Mehul
Patel’s Prior Industry
Kwj Engineering
|
Sandisk
|
Verifast Technologies
|
Synaptics
|
Synopsys
|
Dialog Semiconductor
|
Intel
|
Cirrus Logic
Not the Mehul Patel you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Cirrus Logic
Design Verification Engineer
Wed Feb 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Graphics Hardware Engineer
Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Dialog Semiconductor
Senior Design Verification Engineer
Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
ASIC Digital Design Engr , Sr I
Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Synaptics
Sr. Asic Verification Engineer
Fri Feb 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Sandisk
Product Engineering Intern
Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Verifast Technologies
VERIFICATION TRAINING
Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Kwj Engineering
Engineering Intern
Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)