
Michael Hooks
At Intel Corporation, my role as Manager of PV CAD Signoff for STA (Static Timing Analysis) and Principal... | Austin, Texas, United States
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Michael Hooks’s Emails mi****@in****.com
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Michael Hooks’s Location Austin, Texas, United States
Michael Hooks’s Expertise At Intel Corporation, my role as Manager of PV CAD Signoff for STA (Static Timing Analysis) and Principal Engineer centers on enhancing CPU design through advanced tool and flow development. I worked across both standard cell based designs and transistor-level designs. We focus on crafting state-of-the-art EDA CAD methodologies, which has been instrumental in propelling high-speed CPU projects to success. My leadership in the CAD Signoff team is marked by a dedication to innovation and mentorship, backed by over multiple years of driving performance verification efforts and double-digit project tapeouts. Beyond managing the team, I specialize in path planning and IP development, incorporating my technical acumen to refine our design automation processes. This hands-on approach has yielded robust tools that bolster the design and verification stages, ensuring our CPUs meet the rigorous demands of the technology landscape. My commitment to excellence is rooted in a career-long pursuit of creating impactful solutions and fostering growth within my team. I'm proud to have mentored various folks throughout the years in STA, PrimeTime, Perl, and even enabled some of my employees to get promoted. I love to automate various process and skilled in Perl, Python and Tcl. I love sharing what I know to others to help bring out their potential.
Michael Hooks’s Current Industry Intel
Michael
Hooks’s Prior Industry
Advanced Micro Devices
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Intel
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Work Experience

Intel
Manager of PV DA Signoff and Principal Engineer
Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Manager of PV Design Automation Team
Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Sr. CAD/DA Design Engineer
Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Component Design Engineer
Mon Jun 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Advanced Micro Devices
Co-op Assistant CAD Engineer – K7 Design Team
Sun Jan 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time)