
Minchul Kim
Digital design engineer with 14+ years of experience in complex digital IPs and SoC Design • SoC Design & FrontEnd... | Portland, Oregon, United States
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Minchul Kim’s Emails mi****@in****.com
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Minchul Kim’s Location Portland, Oregon, United States
Minchul Kim’s Expertise Digital design engineer with 14+ years of experience in complex digital IPs and SoC Design • SoC Design & FrontEnd (Power, Clock/Reset, DFx, Connectivity, UPF, Static Checks) • Mixed-Signal SerDes IP digital design (PCIe, MPHY, DPHY) • MIPI mobile multimedia interface IPs (DSI, SLIMbus, LLI, MPHY) • Verilog RTL design and digital design methodologies • Strong experience in FPGA validation • Computer architecture and interconnects (ARM, AMBA) • Full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, synthesis, timing closure, post-silicon validation • Linux and Programming Language (Python, C/C++, Perl) • Interpersonal, communication, and writing skills. Able to provide clear and logical presentations and documentation.
Minchul Kim’s Current Industry Intel
Minchul
Kim’s Prior Industry
Samsung Electronics
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Faraday
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Intel
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Work Experience

Intel
SoC Design Engineer
Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Faraday
Staff Digital Design Engineer
Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Faraday
Staff Digital Design Engineer
Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Samsung Electronics
Staff Engineer
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Samsung Electronics
Senior Engineer
Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)