My Tran
Corporate application engineer for Hercules and IC Validator physical verification tools.Main Physical design verification engineer supporting Chip design... | Austin, Austin, United States
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My Tran’s Emails my****@sy****.com
My Tran’s Phone Numbers No phone number available.
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My Tran’s Location Austin, Austin, United States
My Tran’s Expertise Corporate application engineer for Hercules and IC Validator physical verification tools.Main Physical design verification engineer supporting Chip design teams. Worked with Calibre, Mentor Graphics, DRC/LVS physical verification tools. Responsible for verification from cell level to chip level and tape-out.Physical design verification engineer at IBM, worked on Cadence, Avanti and Niagara tools for physical verification DRC/LVS/LPE.
My Tran’s Current Industry IBM Incorporation
My
Tran’s Prior Industry
Sun Microsystems
|
Synopsys Inc.
|
IBM Incorporation
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Work Experience
IBM Incorporation
Physical design verification engineer
Sat Oct 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys Inc.
Staff Corporate Application Engineer
Thu Jul 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Sun Microsystems
Physical Verification Engineer
Mon Jan 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
My Tran Email Addresses
FAQ About My Tran
-
My Tran is located at
Austin, Austin, United States -
My Tran is a
Corporate application engineer for Hercules and IC Validator physical verification tools.Main Physical design verification engineer supporting Chip design teams. Worked with Calibre, Mentor Graphics, DRC/LVS physical verification tools. Responsible for verification from cell level to chip level and tape-out.Physical design verification engineer at IBM, worked on Cadence, Avanti and Niagara tools for physical verification DRC/LVS/LPE. IBM Incorporation -
My Tran currently works in the
IBM Incorporation -
My Tran specializes in
Corporate application engineer for Hercules and IC Validator physical verification tools.Main Physical design verification engineer supporting Chip design teams. Worked with Calibre, Mentor Graphics, DRC/LVS physical verification tools. Responsible for verification from cell level to chip level and tape-out.Physical design verification engineer at IBM, worked on Cadence, Avanti and Niagara tools for physical verification DRC/LVS/LPE. -
My Tran speaks the following languages:
No languages available. -
My Tran has prior experience in the following industries:
IBM Incorporation , Synopsys Inc. , Sun Microsystems -
My Tran has the following professional experience:
IBM Incorporation , Synopsys Inc. , Sun Microsystems . -
You can view My Tran’s
LinkedIn profile at LinkedIn URL. -
My Tran’s work email addresses are
[email protected] . -
My Tran works at
IBM Incorporation
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