Navneet Jain

FAQ About Navneet Jain

• What is Navneet Jain's address?

  Navneet Jain is located at
  Milpitas, California, United States

• What is Navneet Jain's job title?

  Navneet Jain is a
  Currently I am working and leading circuit design activities in the Design Technology Co optimization of next generation sub 28nm technologies(22nm, 14nm, 12nm and 7nm) at Globalfoundries Inc. I design foundation IP's(standard cells , analog building blocks) for early technology evaluation, silicon validation and IP enablement. The works involves circuit design, optimization and innovation using new layout styles, characterization, place and route, testchip development, DFT/ATPG and silicon validation. All my design have 1st time right and qualified with requisite yield at various design exit level. Previously I have worked at AMD, Transmeta, SGI on various projects such as : AMD Fusion Chip, SGI MIPS R12000, R14000, R16000 microprocessors, Origin2000 Server ASIC, Transmeta Efficion Microprocessor, Sony-Toshiba-IBM Cell Microprocessor, IBM Test Chip 65nm SOI, LongRun2 Controller, SRAM Helix Test Chip Toshiba test Chip 32nm , AMD/ATI RV710 Graphics, DTV, HyperTransport RD890, SATA SB800 ASICS Specialties: Advance technology node, FDSOI, FinFET, high performance, low power circuit design, simulation and optimization, chip toplevel integration, interconnect, DFT/ATPG, ESD, logic, and CAD methodologies, scripting : Globalfoundries

• What industry does Navneet Jain currently work in?

  Navneet Jain currently works in the
  Globalfoundries

• What is Navneet Jain's area of expertise?

  Navneet Jain specializes in
  Currently I am working and leading circuit design activities in the Design Technology Co optimization of next generation sub 28nm technologies(22nm, 14nm, 12nm and 7nm) at Globalfoundries Inc. I design foundation IP's(standard cells , analog building blocks) for early technology evaluation, silicon validation and IP enablement. The works involves circuit design, optimization and innovation using new layout styles, characterization, place and route, testchip development, DFT/ATPG and silicon validation. All my design have 1st time right and qualified with requisite yield at various design exit level. Previously I have worked at AMD, Transmeta, SGI on various projects such as : AMD Fusion Chip, SGI MIPS R12000, R14000, R16000 microprocessors, Origin2000 Server ASIC, Transmeta Efficion Microprocessor, Sony-Toshiba-IBM Cell Microprocessor, IBM Test Chip 65nm SOI, LongRun2 Controller, SRAM Helix Test Chip Toshiba test Chip 32nm , AMD/ATI RV710 Graphics, DTV, HyperTransport RD890, SATA SB800 ASICS Specialties: Advance technology node, FDSOI, FinFET, high performance, low power circuit design, simulation and optimization, chip toplevel integration, interconnect, DFT/ATPG, ESD, logic, and CAD methodologies, scripting :

• Which languages does Navneet Jain speak? 

  Navneet Jain speaks the following languages:
  No languages available.

• Which industries has Navneet Jain previously worked in?   

  Navneet Jain has prior experience in the following industries:
  Globalfoundries , Amd , Transmeta , Silicon Graphics , Sgi , Software And Technolgies

• What is Navneet Jain’s work experience?  

  Navneet Jain has the following professional experience:
  Globalfoundries , Globalfoundries , Global Foundries , Amd , Transmeta , Silicon Graphics , Sgi , Software And Technolgies .

• How can I find Navneet Jain on LinkedIn?  

  You can view Navneet Jain’s
  LinkedIn profile at LinkedIn URL.

• What are Navneet Jain’s work email addresses?  

  Navneet Jain’s work email addresses are
  [email protected] .

• What company does Navneet Jain work for?  

  Navneet Jain works at
  Globalfoundries